CXA2089Q/S
A-IN1 (3 each): This bit selects the input signals output to each audio output.
0: Mute
1: Selects the LTV/RTV inputs
2: Selects the LV1/RV1 inputs
3: Selects the LV2/RV2 inputs
4: Selects the LV3/RV3 inputs
5: Selects the LV4/RV4 inputs
6: Mute
7: Mute
AV-IN2 (3): This bit selects the input signals output to output 2 (VOUT2, YOUT2/COUT2, LOUT2/ROUT2).
Note) Both the video output and the audio output are selected at the same time only for AV-IN2.
0: Mute
1: Selects the TV and LTV/RTV inputs
2: Selects the V1, Y1/C1 and LV1/RV1 inputs
3: Selects the V2, Y2/C2 and LV2/RV2 inputs
4: Selects the V3, Y3/C3 and LV3/RV3 inputs
5: Selects the V4 and LV4/RV4 inputs
6: Mute
7: Mute
DC OUT (2): This bit sets the DC voltage output from DC OUT.
0: 4.5V
1: 0V
2: 1.9V
3: 4.5V
3) Status Registers
• When reading two bytes
S
A
A
DATA1
DATA1
A
DATA2
NA P
Slave address
• When reading one byte
S
NA P
Slave address
S: Start condition
A: Acknowledge
NA: No acknowledge
P: Stop condition
When communication is to be terminated in the status register reading mode, the no-acknowledge signal is
needed to assure that the master does not issue the acknowledge signal to the slave.
It is possible to read only DATA1 of the status register by sending the no-acknowledge signal after DATA1.
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SONY [ SONY CORPORATION ]
