CXA2089Q/S
I2C BUS Control Signal
34 SDA
tBUF
33 SCL
tLOW
tR
tHIGH
tF
tSU;DAT
tSU;STA
tSU;STO
tHD;STA
tHD;DAT
P
S
S
P
Fig. 6. I2C BUS Control Signal Timing Chart
Description of Operation
The CXA2089Q/S is a TV I2C bus-compatible AV switch IC. The video system and the stereo audio system
both have 5 inputs and 2 outputs each. 3 of the 5 video system inputs support S2 and S protocols.
The desired inputs can be independently assigned to each output (in the audio system, the left and right
channels are processed as one unit) by I2C bus control. However, the same input is assigned to both the video
and audio system output 2.
I2C BUS Registers
1) I2C BUS
The I2C bus (inter-IC bus) is an inter-IC bus system developed by Philips. Two lines (SDA – serial data, SCL –
serial clock) provide control over start, stop, data transfer, synchronization, and collision avoidance. The IC
outputs are either open collector or open drain, forming a bus line in the wired OR format.
SDA
SCL
A
A
MSB
LSB
MSB
LSB
S
P
1
2
3
4
5
6
7
8
9
1
2
9
S: Start condition; SDA is set "Low" when SCL is "High"
P: Stop condition; SDA is set "High" when SCL is "High"
A: Acknowledge; signal sent from the slave
Data is transmitted by MSB-first. One data unit consists of 8 bits, to which the acknowledge signal, which
1
indicates that the data has been accepted by the slave, is attached at the end. Normally, the slave IC
receives data at the rising edge of SCL and the master 2 IC changes data at the falling edge of SCL.
1
Slave: An IC that is placed under the control of the master. In a normal system, all devices excluding the
central microcomputer are slaves.
2
Master: A central microcomputer or other controlling IC.
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SONY [ SONY CORPORATION ]
