CXA2066S
Description of Operation
1. Sharpness function
The RGB signals input to Pins 7, 9, and 11 are mixed at a ratio of 0.6G + 0.3R + 0.1B to form the Y signal. The
high-frequency component is removed from this Y signal by a differentiation circuit, and the amplitude is
controlled by a gain control circuit. The signal which undergoes gain control (sharpness component) has its
amplitude clipped by a limiter circuit and is then added to the R, G, and B signals.
SHP GAIN = 0 (HEX)
or SHP OFF = 1
No sharpness component
Section not sent to RGB output because of the limiter
Limiter level = 30% (Typ.)
100%
100%
SHP GAIN = F (HEX)
10%
50ns
(T SW = 0)
100ns
(T SW = 1)
RGB output when RIN = GIN = BIN = 0.7Vp-p
The output level is set to 100%.
2. VBLK synchronous DAC refresh system
The VBLK signal is removed from the composite BLK signal which has been input to Pin 18, and the data for
each control DAC is overwritten all at once in synchronization with this VBLK signal. The received I2C bus data
is held by a latch until the next VBLK signal arrives. As a result, I2C bus data transmission from the
microcomputer is timing-free. Set the V blanking pulse width which is input to Pin 18 at 300µs or more.
– 16 –
SONY [ SONY CORPORATION ]
