CXA2066S
I2C BUS Logic System
No.
Item
High level input voltage
Low level input voltage
Symbol
Min.
3.0
0
Typ.
—
Max.
5.0
Unit
V
1
2
VIH
VIL
—
1.5
V
Low level output voltage
SDA, during current inflow of 3mA
3
VOL
0
—
0.4
V
4
5
6
7
8
9
Maximum clock frequency
fSCL
0
—
—
—
—
—
—
—
—
—
—
—
100
—
—
—
—
—
—
—
1
kHz
µs
µs
µs
µs
µs
ns
ns
µs
ns
µs
Minimum waiting time for data change
Minimum waiting time for data transfer start
Low level clock pulse width
t
t
t
t
t
t
t
t
t
t
BUF
4.0
4.0
4.7
4.0
4.7
440
250
—
HD; STA
LOW
High level clock pulse width
HIGH
Minimum waiting time for start preparation
SU; STA
HD; DAT
SU; DAT
R
10 Minimum data hold time
11 Minimum data preparation time
12 Rise time
13 Fall time
F
—
300
—
14 Minimum waiting time for stop preparation
SU; STO
4.7
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SONY [ SONY CORPORATION ]
