CXA2013M
I2C Bus Block Items (SDA, SCL)
No.
1
Item
Symbol
VIH
Min.
3.0
0
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
5.0
1.5
10
10
0.4
—
Unit
V
High level input voltage
VIL
2
Low level input voltage
IIH
—
3
High level input current
µA
IIL
—
4
Low level input current
V
VOL
0
5
Low level output voltage SDA (Pin 8) during 3mA inflow
Maximum inflow current
mA
pF
IOL
3
6
CI
—
10
100
—
7
Input capacitance
kHz
fSCL
0
8
Maximum clock frequency
Minimum waiting time for data change
tBUF
4.7
4.0
4.7
4.0
4.7
0
9
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
—
10 Minimum waiting time for start of data transfer
11 Low level clock pulse width
12 High level clock pulse width
13 Minimum waiting time for start preparation
14 Minimum data hold time
—
µs
—
—
—
ns
µs
ns
µs
250
—
—
15 Minimum data preparation time
16 Rise time
1
tF
—
300
—
17 Fall time
tSU:STO
4.7
18 Minimum waiting time for stop preparation
I2C bus load conditions: Pull-up resistor 4kΩ (Connect to +5V)
Load capacitor 200pF (Connect to GND)
I2C Bus Control Signal
SDA
t
BUF
t
HD:STA
t
R
tF
SCL
t
SU:STO
t
SU:STA
t
HIGH
Sr
P
P
tLOW
t
HD:STA
t
SU:DAT
S
t
HD:DAT
– 18 –
SONY [ SONY CORPORATION ]
