CXA2013M
• I2C data write (Write from I2C controller to the IC)
L during Write
Hi-Z
MSB
MSB
1
LSB
8
Hi-Z
SDA
1
2
3
Address
Hi-Z
4
5
6
7
8
9
9
SCL
S
ACK
Sub Address
ACK
MSB
LSB
Hi-Z
1
8
9
1
8
9
DATA (n)
ACK
DATA (n + 1)
ACK
DATA (n + 2)
Hi-Z
Hi-Z
Data can be transferred in 8-bit units to be
set as required.
8
9
1
8
9
Sub address is incremented automatically.
P
DATA
ACK
DATA
ACK
• I2C data read (Read from the IC to I2C controller)
H during Read
Hi-Z
SDA
SCL
1
6
7
8
9
1
8
9
7
S
P
Address
ACK
DATA
ACK
• Read timing
IC output SDA
SCL
MSB
LSB
9
9
1
2
3
4
5
6
7
8
Read timing
ACK
DATA
ACK
Data Read is performed during SCL rise.
– 20 –
SONY [ SONY CORPORATION ]
