USB 2.0 HSIC Hi-Speed 4-Port Hub Controller
Datasheet
write operation. Where color is visible in the figure, blue indicates signaling from the I2C master, and
gray indicates signaling from the slave.
S
7-Bit Slave Address
0
A
xxxxxxxx
A
nnnnnnnn
A
...
nnnnnnnn
A
P
Register
Address
(bits 7-0)
Data value for
XXXXXX
Data value for
XXXXXX + y
Figure 7.7 I2C Sequential Access Write Format
In this operation, following the 7-bit slave address, the 8-bit register address is written indicating the
start address for sequential write operation. Every subsequent access is a data write to a data register,
where the register address increments after each access and an ACK from the slave occurs.
Sequential write access is terminated by a Stop condition.
7.2.1.2
Sequential Access Reads
The I2C interface supports direct reading of the device registers. In order to read one or more register
addresses, the starting address must be set by using a write sequence followed by a read. The read
register interface supports auto-increment mode. The master must send a NACK instead of an ACK
when the last byte has been transferred.
In this operation, following the 7-bit slave address, the 8-bit register address is written indicating the
start address for the subsequent sequential read operation. In the read sequence, every data access
is a data read from a data register where the register address increments after each access. The write
sequence can end with optional Stop (P). If so, the read sequence must begin with a Start (S).
Otherwise, the read sequence must start with a Repeated Start (Sr).
Figure 7.8 shows the format of the read operation. Where color is visible in the figure, blue and gold
indicate signaling from the I2C master, and gray indicates signaling from the slave.
Optional. If present, Next
access must have Start(S),
otherwise Repeat Start (Sr)
S
7-Bit Slave Address
0
A
xxxxxxxx
A
P
Register
Address
(bits 7-0)
If previous write setting up
Register address ended with a
Stop (P), otherwise it will be
Repeated Start (Sr)
S
7-Bit Slave Address
1
ACK n n n n n n n n ACK n n n n n n n n ACK
...
n n n n n n n n NACK
P
Register value
for xxxxxxxx
Register value
for xxxxxxxx + 1
Register value
for xxxxxxxx + y
Figure 7.8 I2C Sequential Access Read Format
SMSC USB4604
39
Revision 1.0 (06-17-13)
DATASHEET
SMSC [ SMSC CORPORATION ]
