USB 2.0 HSIC Hi-Speed 4-Port Hub Controller
Datasheet
Table 7.3 Upstream Custom Battery Charger Control Register (continued)
UP_CUST_BC_CTL
(0x30E3 - RESET= 0x00)
UPSTREAM CUSTOM BATTERY CHARGING CONTROL
BIT
NAME
R/W
DESCRIPTION
0
SeRxEn
R/W
Single-ended receiver control
0: Single-ended receiver disabled
1: Single-ended receiver enabled
Table 7.4 Upstream Custom Battery Charger Status Register
UPSTREAM CUSTOM BATTERY CHARGING STATUS
UP_CUST_BC_STAT
(0x30E4 - RESET= 0x00)
BIT
NAME
R/W
DESCRIPTION
7:4
3
Reserved
RxHiCurr
R
R
Reserved
DM high current Apple charger output
0: DM signal is not above the VSE_RXH threshold
1: DM signal is above the VSE_RXH threshold
2
1
0
DmSeRx
DpSeRx
VdatDet
R
R
R
DM Single Ended Receiver Status
DP Single Ended Receiver Status
Vdat detect
0: Vdat not detected
1: Vdat detect comparator output
Table 7.5 Port Power Status Register
PORT POWER STATUS
PORT_PWR_STAT
(0x30E5 - RESET= 0x00)
BIT
NAME
R/W
DESCRIPTION
7:5
4:1
Reserved
R
R
Reserved
PRTPWR[4:1]
Optional status to SOC indicating that power to the corresponding
downstream port was enabled by the USB Host for the specified port. Not
required for an embedded application.
This is a read-only status bit. Actual control over port power is
implemented by the USB Host, OCS Status Register and Downstream
Battery Charging logic, if enabled.
0: USB Host has not enabled port to be powered or in downstream battery
charging and corresponding OCS bit has been set
1: USB Host has enabled port to be powered
0
Reserved
R
Reserved
SMSC USB4604
43
Revision 1.0 (06-17-13)
DATASHEET
SMSC [ SMSC CORPORATION ]
