USB 2.0 HSIC Hi-Speed 4-Port Hub Controller
Datasheet
7.1.8
JEDEC-ID Read Example
To perform a JEDEC-ID command, the device writes 0x9F into the first byte of the SPI_CMD_BUF.
The length of the transfer is 4 bytes. The device first drives SPI_CE_N low, then SPI_DO is output
with 8 bits of the command, followed by the 24 bits of dummy bytes (due to the length being set to 4).
When the transfer is complete, SPI_CE_N goes high. After the first byte, the data on SPI_DI is clocked
into the SPI_RSP_BUF. At the end of the command, there are three valid bytes in the SPI_RSP_BUF.
In this example, 0xBF, 0x25, 0x8E.
SPI_CE_N
SPI_CLK
0
4
5 6
9 10 1112 1314 15 16 17 18 19 20 2122 2324 25 26 272829 30 31 32 33 34
1
2
3
7
8
SPI_DO
SPI_DI
9F
MSB
HIGH IMPEDANCE
8E
BF
25
MSB
MSB
Figure 7.6 SPI JEDEC-ID Read Sequence
7.2
I2C Master Interface
The I2C master interface implements a subset of the I2C Master Specification (Please refer to the
Philips Semiconductor Standard I2C-Bus Specification for details on I2C bus protocols). The device’s
I2C master interface conforms to the Standard-Mode I2C Specification (100 kbit/s transfer rate and 7-
bit addressing) for protocol and electrical compatibility. The device acts as the master and generates
the serial clock SCL, controls the bus access (determines which device acts as the transmitter and
which device acts as the receiver), and generates the START and STOP conditions.
Note: Extensions to the I2C Specification are not supported.
Note: All device configuration must be performed via the SMSC Pro-Touch Programming Tool. For
additional information on the Pro-Touch programming tool, contact your local SMSC sales
representative.
2
7.2.1
I C Message Format
7.2.1.1
Sequential Access Writes
The I2C interface supports sequential writing of the device’s register address space. This mode is
useful for configuring contiguous blocks of registers. Figure 7.7 shows the format of the sequential
Revision 1.0 (06-17-13)
38
SMSC USB4604
DATASHEET
SMSC [ SMSC CORPORATION ]
