TABLE OF CONTENTS
1
2
PIN CONFIGURATIONS....................................................................................................................... 6
PIN DESCRIPTION ............................................................................................................................... 8
2.1
2.2
2.3
BUFFER TYPE PER PIN...................................................................................................................... 8
BUFFER TYPE SUMMARY ................................................................................................................. 12
OUTPUT DRIVERS ........................................................................................................................... 12
3
3.1
4
FUNCTIONAL DESCRIPTION............................................................................................................ 14
HOST PROCESSOR INTERFACE ........................................................................................................ 14
SERIAL PORT (UART) ....................................................................................................................... 15
REGISTER DESCRIPTION ................................................................................................................. 15
4.1
4.1.1
RECEIVE BUFFER REGISTER (RB) ................................................................................... 15
TRANSMIT BUFFER REGISTER (TB)................................................................................. 15
INTERRUPT ENABLE REGISTER (IER).............................................................................. 15
INTERRUPT IDENTIFICATION REGISTER (IIR) ................................................................ 16
FIFO CONTROL REGISTER (FCR) ..................................................................................... 17
LINE CONTROL REGISTER (LCR)...................................................................................... 18
MODEM CONTROL REGISTER (MCR)............................................................................... 19
LINE STATUS REGISTER (LSR) ......................................................................................... 20
MODEM STATUS REGISTER (MSR) .................................................................................. 21
SCRATCHPAD REGISTER (SCR)....................................................................................... 21
PROGRAMMABLE BAUD RATE GENERATOR DIVISOR LATCHES ................................ 21
The Affects of RESET on the UART Registers..................................................................... 22
FIFO INTERRUPT MODE OPERATION................................................................................................ 23
FIFO POLLED MODE OPERATION .................................................................................................... 23
NOTES ON SERIAL PORT FIFO MODE OPERATION ........................................................................... 25
GENERAL ............................................................................................................................. 25
TX AND RX FIFO OPERATION............................................................................................ 25
4.1.2
4.1.3
4.1.4
4.1.5
4.1.6
4.1.7
4.1.8
4.1.9
4.1.10
4.1.11
4.1.12
4.2
4.3
4.4
4.4.1
4.4.2
5
PARALLEL PORT............................................................................................................................... 27
5.1
IBM XT/AT COMPATIBLE, BI-DIRECTIONAL AND EPP MODES.............................................. 28
5.1.1
DATA PORT.......................................................................................................................... 28
STATUS PORT ..................................................................................................................... 28
CONTROL PORT.................................................................................................................. 29
EPP ADDRESS PORT.......................................................................................................... 29
EPP DATA PORT 0............................................................................................................... 29
EPP DATA PORT 1............................................................................................................... 29
EPP DATA PORT 2............................................................................................................... 30
EPP DATA PORT 3............................................................................................................... 30
EPP 1.9 OPERATION................................................................................................................... 30
Software Constraints............................................................................................................. 30
EPP 1.9 Write........................................................................................................................ 30
EPP 1.9 Read........................................................................................................................ 31
EPP 1.7 OPERATION................................................................................................................... 31
Software Constraints............................................................................................................. 31
EPP 1.7 Write........................................................................................................................ 31
EPP 1.7 Read........................................................................................................................ 32
EXTENDED CAPABILITIES PARALLEL PORT........................................................................... 33
Vocabulary ............................................................................................................................ 33
ISA IMPLEMENTATION STANDARD................................................................................... 34
Description ............................................................................................................................ 34
Register Definitions ............................................................................................................... 35
OPERATION ......................................................................................................................... 39
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
5.1.7
5.1.8
5.2
5.2.1
5.2.2
5.2.3
5.3
5.3.1
5.3.2
5.3.3
5.4
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
SMSC DS – SP37E760
Page 3
Rev. 04/13/2001
SMSC [ SMSC CORPORATION ]
