3
FUNCTIONAL DESCRIPTION
Super I/O Registers
Table 3 shows the addresses of the various device blocks of the Super I/O immediately after power up. The base
addresses must be set in the configuration registers before accessing these devices. The base addresses of the Serial
and Parallel Ports can be moved via the configuration registers.
3.1 Host Processor Interface
The host processor communicates with the SP37E760 using the Super I/O registers. Register access is
accomplished through programmed I/O or DMA transfers. All registers are 8 bits wide. All host interface output
buffers are capable of sinking a minimum of 12 mA.
Table 3 - SP37E760 Block Addresses
ADDRESS
3F0, 3F1 or 370, 371
Base +[0:7]
Base1 +[0:7]
Base2 +[0:7]
BLOCK NAME
Configuration
NOTES
Write only; Note 1
Serial Port Com 1
Serial Port Com 2
Disabled at power up; Note 2
Disabled at power up; Note 2
Base +[0:3] all modes
Base +[4:7] for EPP
Base +[400:403] for ECP
Parallel Port
Disabled at power up; Note 2
Note 1: Configuration registers can only be modified in the configuration state, refer to section CONFIGURATION on
page 45 for more information. All logical blocks in the SP37E760 can operate normally in the Configuration
State.
Note 2: The base addresses must be set in the configuration registers before accessing the logical device blocks.
SMSC DS – SP37E760
Page 14
Rev. 04/13/2001
SMSC [ SMSC CORPORATION ]
