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LPC47M182-NR 参数 Datasheet PDF下载

LPC47M182-NR图片预览
型号: LPC47M182-NR
PDF下载: 下载PDF文件 查看货源
内容描述: 先进的I / O控制器,主板胶合逻辑 [ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC]
分类和应用: 控制器
文件页数/大小: 223 页 / 1215 K
品牌: SMSC [ SMSC CORPORATION ]
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Advanced I/O Controller with Motherboard GLUE Logic  
Datasheet  
Table 6.21 - Skip Bit vs. Read Deleted Data Command  
RESULTS  
DATA ADDRESS  
MARK TYPE  
SK BIT  
VALUE  
SECTOR CM BIT OF  
DESCRIPTION  
OF RESULTS  
ENCOUNTERED  
READ?  
ST2 SET?  
0
Normal Data  
Yes  
Yes  
Address not  
incremented. Next  
sector not  
searched for.  
Normal  
0
1
Deleted Data  
Normal Data  
Yes  
No  
No  
termination.  
Normal  
Yes  
termination.  
Sector not read  
(“skipped”).  
Normal  
termination.  
1
Deleted Data  
Yes  
No  
6.13 Read A Track  
This command is similar to the Read Data command except that the entire data field is read continuously  
from each of the sectors of a track. Immediately after encountering a pulse on the nINDEX pin, the FDC  
starts to read all data fields on the track as continuous blocks of data without regard to logical sector  
numbers. If the FDC finds an error in the ID or DATA CRC check bytes, it continues to read data from the  
track and sets the appropriate error bits at the end of the command. The FDC compares the ID  
information read from each sector with the specified value in the command and sets the ND flag of Status  
Register 1 to a “1” if there no comparison. Multi-track or skip operations are not allowed with this  
command. The MT and SK bits (bits D7 and D5 of the first command byte respectively) should always be  
set to “0”.  
This command terminates when the EOT specified number of sectors has not been read. If the FDC does  
not find an ID Address Mark on the diskette after the second occurrence of a pulse on the nINDEX pin,  
then it sets the IC code in Status Register 0 to “01” (abnormal termination), sets the MA bit in Status  
Register 1 to “1”, and terminates the command.  
Table 6.22 - Result Phase Table  
FINAL SECTOR  
TRANSFERRED TO  
HOST  
MT  
HEAD  
ID INFORMATION AT RESULT PHASE  
C
H
R
N
0
0
1
0
1
Less than EOT  
Equal to EOT  
Less than EOT  
Equal to EOT  
Less than EOT  
Equal to EOT  
Less than EOT  
Equal to EOT  
NC  
C + 1  
NC  
C + 1  
NC  
NC  
NC  
C + 1  
NC  
NC  
NC  
NC  
NC  
LSB  
NC  
LSB  
R + 1  
01  
R + 1  
01  
R + 1  
01  
R + 1  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
1
01  
NC: No Change, the same value as the one at the beginning of command execution.  
LSB: Least Significant Bit, the LSB of H is complemented.  
SMSC LPC47M182  
67  
Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)  
DATASHEET  
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