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LPC47S45X 参数 Datasheet PDF下载

LPC47S45X图片预览
型号: LPC47S45X
PDF下载: 下载PDF文件 查看货源
内容描述: 先进的I / O与X -Bus接口 [Advanced I/O with X-Bus Interface]
分类和应用:
文件页数/大小: 259 页 / 1575 K
品牌: SMSC [ SMSC CORPORATION ]
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6.7.4 EXTENDED CAPABILITIES PARALLEL PORT  
ECP provides a number of advantages, some of which are listed below. The individual features are explained in greater  
detail in the remainder of this section.  
High performance half-duplex forward and reverse channel Interlocked handshake, for fast reliable transfer Optional  
single byte RLE compression for improved throughput (64:1) Channel addressing for low-cost peripherals Maintains link  
and data layer separation Permits the use of active output drivers permits the use of adaptive signal timing Peer-to-peer  
capability.  
6.7.5 VOCABULARY  
The following terms are used in this document:  
assert: When a signal asserts it transitions to a "true" state, when a signal deasserts it transitions to a "false" state.  
forward: Host to Peripheral communication.  
reverse: Peripheral to Host communication  
Pword: A port word; equal in size to the width of the LPC interface. For this implementation, PWord is always 8 bits.  
1
0
A high level.  
A low level.  
These terms may be considered synonymous:  
-
-
-
-
-
-
-
-
-
PeriphClk, nAck  
HostAck, nAutoFd  
PeriphAck, Busy  
nPeriphRequest, nFault  
nReverseRequest, nInit  
nAckReverse, PError  
Xflag, Select  
ECPMode, nSelectln  
HostClk, nStrobe  
Reference Document: IEEE 1284 Extended Capabilities Port Protocol and ISA Interface Standard, Rev 1.14, July 14,  
1993. This document is available from Microsoft.  
The bit map of the Extended Parallel Port registers is:  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
Note  
data  
PD7  
PD6  
PD5  
PD4  
PD3  
PD2  
PD1  
PD0  
ecpAFifo Addr/RLE  
Address or RLE field  
Select nFault  
2
1
1
2
2
2
dsr  
nBusy  
0
nAck  
0
PError  
0
0
0
dcr  
Direction ackIntEn SelectIn  
Parallel Port Data FIFO  
ECP Data FIFO  
nInit  
autofd  
strobe  
cFifo  
ecpDFifo  
tFifo  
Test FIFO  
cnfgA  
cnfgB  
ecr  
0
0
0
1
0
0
0
0
compress intrValue  
MODE  
Parallel Port IRQ  
Parallel Port DMA  
full empty  
nErrIntrEn dmaEn serviceIntr  
Note 1: These registers are available in all modes.  
Note 2: All FIFOs use one common 16 byte FIFO.  
Note 3: The ECP Parallel Port Config Reg B reflects the IRQ and DRQ selected by the Configuration Registers.  
6.7.6 ECP IMPLEMENTATION STANDARD  
This specification describes the standard interface to the Extended Capabilities Port (ECP). All LPC devices supporting  
ECP must meet the requirements contained in this section or the port will not be supported by Microsoft. For a  
description of the ECP Protocol, please refer to the IEEE 1284 Extended Capabilities Port Protocol and ISA Interface  
Standard, Rev. 1.14, July 14, 1993. This document is available from Microsoft.  
Description  
SMSC DS – LPC47S45x  
Page 83 of 259  
Rev. 07/09/2001  
DATASHEET  
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