Table 31 − Reset Function Table
REGISTER/SIGNAL
Interrupt Enable Register
Interrupt Identification Reg.
FIFO Control
RESET CONTROL
RESET STATE
RESET
All bits low
RESET
Bit 0 is high; Bits 1 - 7 low
RESET
All bits low
Line Control Reg.
RESET
All bits low
MODEM Control Reg.
Line Status Reg.
RESET
All bits low
RESET
All bits low except 5, 6 high
MODEM Status Reg.
TXD1, TXD2
RESET
Bits 0 - 3 low; Bits 4 - 7 input
RESET
High
INTRPT (RCVR errs)
RESET/Read LSR
Low
INTRPT (RCVR Data Ready) RESET/Read RBR
Low
INTRPT (THRE)
OUT2B
RESET/ReadIIR/Write THR
Low
RESET
High
RTSB
RESET
High
DTRB
RESET
High
OUT1B
RESET
High
RCVR FIFO
RESET/
All Bits Low
FCR1*FCR0/_FCR0
RESET/
All Bits Low
XMIT FIFO
FCR1*FCR0/_FCR0
SMSC DS – LPC47S45x
Page 72 of 259
Rev. 07/09/2001
DATASHEET
SMSC [ SMSC CORPORATION ]
