VTR Power On Elapsed Time Counter registers at offset 0x71 to 0x74.
Power Supply Control Register at Logical Device A at offset 0xF8
Power Management 1 Status Register 1 at offset 0x78
Power Management 1 Status Register 2 at offset 0x79
Power Management 1 Enable Register 1 at offset 0x7A
Power Management 1 Enable Register 2 at offset 0x7B
Power Management 1 Control Register 1 at offset 0x60
Power Management 1 Control Register 2 at offset 0x61
General Purpose Event 1 Enable Register 1 at offset 0x7E
General Purpose Event 1 Enable Register 2 at offset 0x7F
Note: All Vbat powered pins and registers are powered by VTR when VTR power is on and are battery backed-up
when VTR is removed.
5.3 Internal PWRGOOD
An internal PWRGOOD logical control is included to minimize the effects of pin-state uncertainty in the host interface
as Vcc cycles on and off. When the internal PWRGOOD signal is “1” (active), Vcc > 2.3V (nominal), and the
LPC47S45x host interface is active. When the internal PWRGOOD signal is “0” (inactive), Vcc ≤ 2.3V (nominal), and
the LPC47S45x host interface is inactive; that is, LPC bus reads and writes will not be decoded.
The LPC47S45x device pins nPB_IN, IO_PME#, XTAL2/CLKI32 and XTAL1, KDAT, MDAT, IRRX, nRI1, nRI2,
RXD2, Fan_Tach, and most GPIOs (as input) are part of the PME interface and remain active when the internal
PWRGOOD signal has gone inactive, provided VTR is powered. The nPS_ON, CLKO40, GP53/TXD2/IRTX,
GP60/LED1 and GP61/LED2 pins also remain active when the internal PWRGOOD signal has gone inactive,
provided VTR is powered. See Trickle Power Functionality section.
5.4 32.768 KHZ Trickle Clock Input
The LPC47S45x has three different methods of deriving a 32.768kHz signal:
From an external crystal oscillator connected accross pins XTAL1 and XTAL2
From an external single-input clock source driven on the CLKI32 pin
From an internal PLL that divides down the14MHz clock input to make the 32kHz signal
The trickle clock input is used to supply a clock signal for the RTC, 40 MHz clock output, fan tachometer logic, WDT,
LED blink and wake on specific key function. See the following section for more information.
5.5 Indication of 32KHZ Clock
There is a bit to indicate whether the 32kHz clock signal is taken from an external 32kHz clock source or derived
internally from the 14MHz clock input. This bit is located at Bit[0] of the Clock Select register at 0xF0 in Logical
Device A and is referred to as CLK32_PRSN. This register is powered by VTR and reset on a VTR POR.
Bit[0] (CLK32_PRSN) is defined as follows:
0 = Either a single-input 32kHz clock is connected to the CLKI32 pin or a crystal oscillator is connected to the
XTAL1and XTAL2 pins (crystal oscillator is default case).
Note: The XOSEL pin must be pulled-up if a single-input 32kHz clock source is used. See section 5.6 XOSEL.
1 = Neither the 32kHz clock nor the crystal oscillator are connected.
Note: When Bit[0]=1, the 32kHz clock is derived internally from the 14MHz clock input.
Note: An external crystal oscillator must be supplied to generate the 32.768kHz clock input for the RTC block under
Vbat power.
SMSC DS – LPC47S45x
Page 20 of 259
Rev. 07/09/2001
DATASHEET
SMSC [ SMSC CORPORATION ]
