REG OFFSET
(hex)
NAME
DESCRIPTION
General Purpose I/0 Data Register 5
Bit[0] GP50
GP5
4F
Default = 0x00
on VTR POR
Bit 3 is reset on VCC
POR, Hard Reset
and VTR POR
(R/W)
Bit[1] GP51
Bit[2] GP52
Bit[3] GP53
Bit[4] GP54
Bit[5] GP55
Bit[6] GP56
Bit[7] GP57
GP6
50
General Purpose I/0 Data Register 6
Bit[0] GP60
Default = 0x00
on VTR POR
N/A
(R/W)
Bit[1] GP61
Bit[7:2] Reserved
Reserved – reads return 0
51
(R)
52
N/A
Reserved – reads return 0
(R)
53
N/A
Reserved – reads return 0
(R)
54
INT_GEN1
Default = 0xFF
Interrupt Generating Register 1 (Note 8)
0=Corresponding Interrupt frame driven low in the SER
IRQ stream. This must be enabled through the INT_G
Configuration Register.
(R/W)
on VCC POR and
Bit[0] Reserved
Bit[1] nINT1
Bit[2] nINT2
Bit[3] nINT3
Bit[4] nINT4
Bit[5] nINT5
Bit[6] nINT6
Bit[7] nINT7
HARD RESET
Note: To enable/disable this register see Logical
Device A (0xF1)
Interrupt Generating Register 2 (Note 8)
INT_GEN2
55
0=Corresponding Interrupt frame driven low in the SER
IRQ stream. This must be enabled through the INT_G
Configuration Register.
Default = 0xFF
(R/W)
on VCC POR and
Bit[0] nINT8
Bit[1] nINT9
Bit[2] nINT10
Bit[3] nINT11
Bit[4] nINT12
Bit[5] nINT13
Bit[6] nINT14
Bit[7] nINT15
HARD RESET
Note: To enable/disable this register see Logical
Device A (0xF1)
SMSC DS – LPC47M14X
Page 147
Rev. 03/19/2001
SMSC [ SMSC CORPORATION ]
