REGISTER
OFFSET
HARD
SOFT
(hex)
5A
5B
5C
5D
5E
5F
60-7F
RESET
RESET
TYPE
R
VCC POR
VTR POR
0x00
0x00
0x00
0x00
0x00
0x00
-
REGISTER
Fan2 Tachometer Register
Fan1 Preload Register
Fan2 Preload Register
LED1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W
R/W
R/W
R/W
R/W
R
LED2
Keyboard Scan Code
Reserved – reads return 0
Note 1: This register is read-only when GP43 register bit [3:2] = 01 and the GP43 pin is high.
Note 2: Bits [3:2] of this register are reset (cleared) on VCC POR and Hard Reset (and VTR POR).
Note 3: Bit 3 of this register is reset (cleared) on VCC POR and Hard Reset (and VTR POR).
Note 4: The parallel port interrupt defaults to 1 when the parallel port activate bit is cleared.
Note 5: Bits 2 and 3 of the PME_STS4 and SMI_STS4 registers, and bit 3 of the PME_STS5 register may be set on a
VCC POR. If GP32, GP33 and GP53 are configured as input, then their corresponding PME and SMI status bits will be
set on a VCC POR Also, GP32 and GP33 pins revert to their non-inverting GPIO input function when VCC is removed
from the part. These GPIOs cannot be used for PME wakeup when the part is under VTR power (VCC=0).
The following registers are located at an offset from (PME_BLK) the address programmed into the base I/O address
register for Logical Device A.
Table 59 – PME, SMI, GPIO, FAN Register Description
REG OFFSET
(hex)
NAME
PME_STS
DESCRIPTION
00
Bit[0] PME_Status
= 0 (default)
Default = 0x00
on VTR POR
(R/W)
= 1 Set when LPC47M14x would normally assert the
nIO_PME signal, independent of the state of the
PME_En bit.
Bit[7:1] Reserved
PME_Status is not affected by Vcc POR, SOFT RESET
or HARD RESET.
Writing a “1” to PME_Status will clear it and cause the
LPC47M14x to stop asserting nIO_PME, in enabled.
Writing a “0” to PME_Status has no effect.
N/A
01
(R)
02
Reserved – reads return 0
PME_EN
Bit[0] PME_En
= 0 nIO_PME signal assertion is disabled (default)
= 1 Enables LPC47M14x to assert nIO_PME signal
Bit[7:1] Reserved
Default = 0x00
on VTR POR
(R/W)
PME_En is not affected by Vcc POR, SOFT RESET or
HARD RESET
Reserved – reads return 0
N/A
03
(R)
SMSC DS – LPC47M14X
Page 127
Rev. 03/19/2001
SMSC [ SMSC CORPORATION ]
