REG OFFSET
(hex)
NAME
PME_STS1
DESCRIPTION
PME Wake Status Register 1
04
This register indicates the state of the individual PME
wake sources, independent of the individual source
enables or the PME_En bit.
Default = 0x00
on VTR POR
(R/W)
If the wake source has asserted a wake event, the
associated PME Wake Status bit will be a “1”.
Bit[0] Reserved (Note 7)
Bit[1] RI2
Bit[2] RI1
Bit[3] KBD
Bit[4] MOUSE
Bit[5] SPEKEY (Wake on specific key)
Bit[6] FAN_TACH1
Bit[7] FAN_TACH2
The PME Wake Status register is not affected by Vcc
POR, SOFT RESET or HARD RESET.
Writing a “1” to Bit[7:0] will clear it. Writing a “0” to any
bit in PME Wake Status Register has no effect.
PME Wake Status Register 2
PME_STS2
05
This register indicates the state of the individual PME
wake sources, independent of the individual source
enables or the PME_En bit.
Default = 0x00
on VTR POR
(R/W)
If the wake source has asserted a wake event, the
associated PME Wake Status bit will be a “1”.
Bit[0] GP10
Bit[1] GP11
Bit[2] GP12
Bit[3] GP13
Bit[4] GP14
Bit[5] GP15
Bit[6] GP16
Bit[7] GP17
The PME Wake Status register is not affected by Vcc
POR, SOFT RESET or HARD RESET.
Writing a “1” to Bit[7:0] will clear it. Writing a “0” to any
bit in PME Wake Status Register has no effect.
PME Wake Status Register 3
PME_STS3
06
This register indicates the state of the individual PME
wake sources, independent of the individual source
enables or the PME_En bit.
Default = 0x00
on VTR POR
(R/W)
If the wake source has asserted a wake event, the
associated PME Wake Status bit will be a “1”.
Bit[0] GP20
Bit[1] GP21
Bit[2] GP22
Bit[3] DEVINT_STS (status of group SMI signal for PME)
Bit[4] GP24
Bit[5] GP25
Bit[6] GP26
Bit[7] GP27
The PME Wake Status register is not affected by Vcc
POR, SOFT RESET or HARD RESET.
Writing a “1” to Bit[7:0] will clear it. Writing a “0” to any
bit in PME Wake Status Register has no effect.
SMSC DS – LPC47M14X
Page 128
Rev. 03/19/2001
SMSC [ SMSC CORPORATION ]
