PCI_CLK
nLFRAME
nLAD[3:0]
L1
L2
Address
Data
TAR
Sync=0110
L3
TAR
FIGURE 12 – I/O WRITE
Note: L1=Start; L2=CYCTYP+DIR; L3=Sync of 0000
PCI_CLK
nLFRAME
L1
L2
Address
TAR
Sync=0110
L3
Data
TAR
nLAD[3:0]
FIGURE 13 – I/O READ
Note: L1=Start; L2=CYCTYP+DIR; L3=Sync of 0000
PCI_CLK
nLDRQ
Start
MSB
LSB
ACT
FIGURE 14 – DMA REQUEST ASSERTION THROUGH nLDRQ
PCI_CLK
nLFRAME
nLAD[3:0]
Start
C+D CHL Size
TAR
Sync=0101
L1
Data
TAR
FIGURE 15 – DMA WRITE (FIRST BYTE)
Note: L1=Sync of 0000
PCI_CLK
nLFRAME
nLAD[3:0]
Start C+D CHL Size
Data
TAR
Sync=0101
L1
TAR
FIGURE 16 – DMA READ (FIRST BYTE)
Note: L1= Sync of 0000
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