FIFO
MODE
ONLY
INTERRUPT
IDENTIFICATION
REGISTER
INTERRUPT SET AND RESET FUNCTIONS
PRIORITY INTERRUPT
INTERRUPT
SOURCE
INTERRUPT
BIT 3
BIT 2 BIT 1 BIT 0
LEVEL
TYPE
RESET
CONTROL
0
0
1
0
Third
Transmitter
Holding
Transmitter
Reading the IIR
Holding Register
Register (if Source
of Interrupt) or
Register Empty Empty
Writing the
Transmitter
Holding Register
Reading the
0
0
0
0
Fourth
MODEM
Status
Clear to Send or
Data Set Ready or MODEM Status
Ring Indicator or
Data Carrier
Detect
Register
LINE CONTROL REGISTER (LCR)
Address Offset = 3H, DLAB = 0, READ/WRITE
Start LSB Data 5-8 bits MSB Parity Stop
Serial Data
This register contains the format information of the serial line. The bit definitions are:
Bits 0 and 1
These two bits specify the number of bits in each transmitted or received serial character. The encoding of bits 0 and 1
is as follows:
The Start, Stop and Parity bits are not included in the word length.
BIT 1
BIT 0
WORD LENGTH
5 Bits
0
0
1
1
0
1
0
1
6 Bits
7 Bits
8 Bits
Bit 2
This bit specifies the number of stop bits in each transmitted or received serial character. The following table
summarizes the information.
NUMBER OF
BIT 2
WORD LENGTH
STOP BITS
0
1
1
1
1
-
1
1.5
2
2
2
5 Bits
6 Bits
7 Bits
8 Bits
Note: The receiver will ignore all stop bits beyond the first, regardless of the number used in transmitting.
Bit 3
Parity Enable bit. When bit 3 is a logic "1", a parity bit is generated (transmit data) or checked (receive data) between
the last data word bit and the first stop bit of the serial data. (The parity bit is used to generate an even or odd number of
1s when the data word bits and the parity bit are summed).
SMSC LPC47B27x
- 59 -
Rev. 08-10-04
DATASHEET
SMSC [ SMSC CORPORATION ]
