Bit[4]: MLATCH – Mouse Interrupt latch control bit. 0=MINT is the 8042 MINT ANDed with Latched
MINT (default), 1=MINT is the latched 8042 MINT.
Bit[3]: KLATCH – Keyboard Interrupt latch control bit. 0=KINT is the 8042 KINT ANDed with Latched
KINT (default), 1=KINT is the latched 8042 KINT.
See the Configuration section for a description of this register.
Keyboard and Mouse PME Generation
The LPC47B27x sets the associated PME Status bits when the following conditions occur:
•
•
•
•
Keyboard Interrupt
Mouse Interrupt
Active Edge on Keyboard Data Signal (KDAT)
Active Edge on Mouse Data Signal (MDAT)
These events can cause a PME to be generated if the associated PME Wake Enable register bit and
the global PME_EN bit are set. Refer to the PME Support section for more details on the PME interface
logic and refer to the Runtime Register section for details on the PME Status and Enable registers.
The keyboard interrupt and mouse interrupt PMEs can be generated when the part is powered by VCC.
The keyboard data and mouse data PMEs can be generated both when the part is powered by VCC,
and when the part is powered by VTR (VCC=0).
When using the keyboard and mouse data signals for wakeup, it may be necessary to isolate the
keyboard signals (KCLK, KDAT, MCLK, MDAT) from the 8042 prior to entering certain system sleep
states. This is due to the fact that the normal operation of the 8042 can prevent the system from
entering a sleep state or trigger false PME events. The LPC47B27x has “isolation” bits for the keyboard
and mouse signals, which allow the keyboard and mouse data signals to go into the wakeup logic but
block the clock and data signals from the 8042. These bits may be used anytime it is necessary to
isolate the 8042 keyboard and mouse signals from the 8042 before entering a system sleep state.
See the SMSC Application Note titled “Using the Enhanced Keyboard and Mouse Wakeup Feature in
SMSC Super I/O Parts” for more information.
The bits used to isolate the keyboard and mouse signals from the 8042 are located in Logical Device 7,
Register 0xF0 (KRST_GA20) and are defined as follows:
Bit[6] M_ISO. Enables/disables isolation of mouse signals into 8042. Does not affect the MDAT signal
to the mouse wakeup (PME) logic.
1=block mouse clock and data signals into 8042
0= do not block mouse clock and data signals into 8042
Bit[5] K_ISO. Enables/disables isolation of keyboard signals into 8042. Does not affect the KDAT
signal to the keyboard wakeup (PME) logic.
1=block keyboard clock and data signals into 8042
0= do not block keyboard clock and data signals into 8042
Note: The M_ISO and K_ISO bits are reset on VTR POR Only.
When the keyboard and/or mouse isolation bits are used, it may be necessary to reset the 8042 upon
exiting the sleep state. If either of the isolation bits is set prior to entering a sleep state where VCC
goes inactive (S3-S5), then the 8042 must be reset upon exiting the sleep mode. Write 0x40 to global
configuration register 0x2C to reset the 8042. The 8042 must then be taken out of reset by writing 0x00
to register 0x2C since the bit that resets the 8042 is not self-clearing. Caution: Bit 6 of configuration
register 0x2C is used to put the 8042 into reset - do not set any of the other bits in register 0x2C, as this
may produce undesired results.
It is not necessary to reset the 8042 if the isolation bits are used for a sleep state where VCC does not
go inactive (S1, S2).
User Note Regarding External Keyboard and Mouse:
This is an application matter resulting from the behavior of the external 8042 in the keyboard.
When the external keyboard and external mouse are powered up, the KDAT and MDAT lines are driven
low. This sets the KBD bit (D3) and the MOUSE bit (D4) of the PME Wake Status Register since the
SMSC LPC47B27x
- 107 -
Rev. 08-10-04
DATASHEET
SMSC [ SMSC CORPORATION ]
