14us
6us
8042
P20
KRST
KBDRST
KRST_GA20
Bit 2
P92
nALT_RST
6us
Bit 0
Pulse
Gen
14us
Note: When Port 92 is disabled,
writes are ignored and reads
return undefined values.
Bit 1 of Port 92, the ALT_A20 signal, is used to force nA20M to the CPU low for support of real mode
compatible software. This signal is externally OR’ed with the A20GATE signal from the keyboard
controller and CPURST to control the nA20M input of the CPU. Writing a 0 to bit 1 of the Port 92
Register forces ALT_A20 low. ALT_A20 low drives nA20M to the CPU low, if A20GATE from the
keyboard controller is also low. Writing a 1 to bit 1 of the Port 92 Register forces ALT_A20 high.
ALT_A20 high drives nA20M to the CPU high, regardless of the state of A20GATE from the keyboard
controller. Upon reset, this signal is driven low.
SMSC LPC47B27x
- 105 -
Rev. 08-10-04
DATASHEET
SMSC [ SMSC CORPORATION ]
