Three Port 10/100 Managed Ethernet Switch with MII
Datasheet
13.2.2.2
13.2.2.3
13.2.2.4
13.2.2.5
13.2.2.6
13.2.2.7
13.2.2.8
13.2.2.9
Port x PHY Basic Status Register (PHY_BASIC_STATUS_x) ..................................................................................................................... 235
Port x PHY Identification MSB Register (PHY_ID_MSB_x).......................................................................................................................... 237
Port x PHY Identification LSB Register (PHY_ID_LSB_x)............................................................................................................................ 238
Port x PHY Auto-Negotiation Advertisement Register (PHY_AN_ADV_x)................................................................................................... 239
Port x PHY Auto-Negotiation Link Partner Base Page Ability Register (PHY_AN_LP_BASE_ABILITY_x) ................................................. 242
Port x PHY Auto-Negotiation Expansion Register (PHY_AN_EXP_x) ......................................................................................................... 244
Port x PHY Mode Control/Status Register (PHY_MODE_CONTROL_STATUS_x)..................................................................................... 245
Port x PHY Special Modes Register (PHY_SPECIAL_MODES_x) .............................................................................................................. 246
13.2.2.10 Port x PHY Special Control/Status Indication Register (PHY_SPECIAL_CONTROL_STAT_IND_x).......................................................... 248
13.2.2.11 Port x PHY Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x)........................................................................................... 250
13.2.2.12 Port x PHY Interrupt Mask Register (PHY_INTERRUPT_MASK_x) ............................................................................................................ 251
13.2.2.13 Port x PHY Special Control/Status Register (PHY_SPECIAL_CONTROL_STATUS_x).............................................................................. 252
13.3 Switch Fabric Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
13.3.1 General Switch CSRs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
13.3.1.1
13.3.1.2
13.3.1.3
13.3.1.4
Switch Device ID Register (SW_DEV_ID) .................................................................................................................................................... 264
Switch Reset Register (SW_RESET) ........................................................................................................................................................... 265
Switch Global Interrupt Mask Register (SW_IMR)........................................................................................................................................ 266
Switch Global Interrupt Pending Register (SW_IPR).................................................................................................................................... 267
13.3.2 Switch Port 0, Port 1, and Port 2 CSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
13.3.2.1
13.3.2.2
13.3.2.3
13.3.2.4
13.3.2.5
13.3.2.6
13.3.2.7
13.3.2.8
13.3.2.9
Port x MAC Version ID Register (MAC_VER_ID_x) ..................................................................................................................................... 268
Port x MAC Receive Configuration Register (MAC_RX_CFG_x)................................................................................................................. 269
Port x MAC Receive Undersize Count Register (MAC_RX_UNDSZE_CNT_x)........................................................................................... 270
Port x MAC Receive 64 Byte Count Register (MAC_RX_64_CNT_x).......................................................................................................... 271
Port x MAC Receive 65 to 127 Byte Count Register (MAC_RX_65_TO_127_CNT_x)................................................................................ 272
Port x MAC Receive 128 to 255 Byte Count Register (MAC_RX_128_TO_255_CNT_x)............................................................................ 273
Port x MAC Receive 256 to 511 Byte Count Register (MAC_RX_256_TO_511_CNT_x)............................................................................ 274
Port x MAC Receive 512 to 1023 Byte Count Register (MAC_RX_512_TO_1023_CNT_x)........................................................................ 275
Port x MAC Receive 1024 to Max Byte Count Register (MAC_RX_1024_TO_MAX_CNT_x) ..................................................................... 276
13.3.2.10 Port x MAC Receive Oversize Count Register (MAC_RX_OVRSZE_CNT_x)............................................................................................. 277
13.3.2.11 Port x MAC Receive OK Count Register (MAC_RX_PKTOK_CNT_x)......................................................................................................... 278
13.3.2.12 Port x MAC Receive CRC Error Count Register (MAC_RX_CRCERR_CNT_x).......................................................................................... 279
13.3.2.13 Port x MAC Receive Multicast Count Register (MAC_RX_MULCST_CNT_x)............................................................................................. 280
13.3.2.14 Port x MAC Receive Broadcast Count Register (MAC_RX_BRDCST_CNT_x)........................................................................................... 281
13.3.2.15 Port x MAC Receive Pause Frame Count Register (MAC_RX_PAUSE_CNT_x) ........................................................................................ 282
13.3.2.16 Port x MAC Receive Fragment Error Count Register (MAC_RX_FRAG_CNT_x)........................................................................................ 283
13.3.2.17 Port x MAC Receive Jabber Error Count Register (MAC_RX_JABB_CNT_x)............................................................................................. 284
13.3.2.18 Port x MAC Receive Alignment Error Count Register (MAC_RX_ALIGN_CNT_x) ...................................................................................... 285
13.3.2.19 Port x MAC Receive Packet Length Count Register (MAC_RX_PKTLEN_CNT_x)..................................................................................... 286
13.3.2.20 Port x MAC Receive Good Packet Length Count Register (MAC_RX_GOODPKTLEN_CNT_x) ................................................................ 287
13.3.2.21 Port x MAC Receive Symbol Error Count Register (MAC_RX_SYMBOL_CNT_x)...................................................................................... 288
13.3.2.22 Port x MAC Receive Control Frame Count Register (MAC_RX_CTLFRM_CNT_x) .................................................................................... 289
13.3.2.23 Port x MAC Transmit Configuration Register (MAC_TX_CFG_x) ................................................................................................................ 290
13.3.2.24 Port x MAC Transmit Flow Control Settings Register (MAC_TX_FC_SETTINGS_x) .................................................................................. 291
13.3.2.25 Port x MAC Transmit Deferred Count Register (MAC_TX_DEFER_CNT_x) ............................................................................................... 292
13.3.2.26 Port x MAC Transmit Pause Count Register (MAC_TX_PAUSE_CNT_x)................................................................................................... 293
13.3.2.27 Port x MAC Transmit OK Count Register (MAC_TX_PKTOK_CNT_x)........................................................................................................ 294
13.3.2.28 Port x MAC Transmit 64 Byte Count Register (MAC_TX_64_CNT_x) ......................................................................................................... 295
13.3.2.29 Port x MAC Transmit 65 to 127 Byte Count Register (MAC_TX_65_TO_127_CNT_x) ............................................................................... 296
13.3.2.30 Port x MAC Transmit 128 to 255 Byte Count Register (MAC_TX_128_TO_255_CNT_x) ........................................................................... 297
13.3.2.31 Port x MAC Transmit 256 to 511 Byte Count Register (MAC_TX_256_TO_511_CNT_x) ........................................................................... 298
13.3.2.32 Port x MAC Transmit 512 to 1023 Byte Count Register (MAC_TX_512_TO_1023_CNT_x) ....................................................................... 299
13.3.2.33 Port x MAC Transmit 1024 to Max Byte Count Register (MAC_TX_1024_TO_MAX_CNT_x)..................................................................... 300
13.3.2.34 Port x MAC Transmit Undersize Count Register (MAC_TX_UNDSZE_CNT_x) .......................................................................................... 301
13.3.2.35 Port x MAC Transmit Packet Length Count Register (MAC_TX_PKTLEN_CNT_x) .................................................................................... 302
13.3.2.36 Port x MAC Transmit Broadcast Count Register (MAC_TX_BRDCST_CNT_x) .......................................................................................... 303
13.3.2.37 Port x MAC Transmit Multicast Count Register (MAC_TX_MULCST_CNT_x) ............................................................................................ 304
13.3.2.38 Port x MAC Transmit Late Collision Count Register (MAC_TX_LATECOL_CNT_x) ................................................................................... 305
13.3.2.39 Port x MAC Transmit Excessive Collision Count Register (MAC_TX_EXCCOL_CNT_x)............................................................................ 306
13.3.2.40 Port x MAC Transmit Single Collision Count Register (MAC_TX_SNGLECOL_CNT_x) ............................................................................. 307
13.3.2.41 Port x MAC Transmit Multiple Collision Count Register (MAC_TX_MULTICOL_CNT_x) ............................................................................ 308
13.3.2.42 Port x MAC Transmit Total Collision Count Register (MAC_TX_TOTALCOL_CNT_x)................................................................................ 309
13.3.2.43 Port x MAC Interrupt Mask Register (MAC_IMR_x) ..................................................................................................................................... 310
13.3.2.44 Port x MAC Interrupt Pending Register (MAC_IPR_x) ................................................................................................................................. 311
13.3.3 Switch Engine CSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
13.3.3.1
13.3.3.2
13.3.3.3
13.3.3.4
13.3.3.5
13.3.3.6
13.3.3.7
13.3.3.8
13.3.3.9
Switch Engine ALR Command Register (SWE_ALR_CMD) ........................................................................................................................ 312
Switch Engine ALR Write Data 0 Register (SWE_ALR_WR_DAT_0).......................................................................................................... 313
Switch Engine ALR Write Data 1 Register (SWE_ALR_WR_DAT_1).......................................................................................................... 314
Switch Engine ALR Read Data 0 Register (SWE_ALR_RD_DAT_0)........................................................................................................... 316
Switch Engine ALR Read Data 1 Register (SWE_ALR_RD_DAT_1)........................................................................................................... 317
Switch Engine ALR Command Status Register (SWE_ALR_CMD_STS) .................................................................................................... 319
Switch Engine ALR Configuration Register (SWE_ALR_CFG) .................................................................................................................... 320
Switch Engine VLAN Command Register (SWE_VLAN_CMD).................................................................................................................... 321
Switch Engine VLAN Write Data Register (SWE_VLAN_WR_DATA).......................................................................................................... 322
13.3.3.10 Switch Engine VLAN Read Data Register (SWE_VLAN_RD_DATA) .......................................................................................................... 323
13.3.3.11 Switch Engine VLAN Command Status Register (SWE_VLAN_CMD_STS) ............................................................................................... 324
13.3.3.12 Switch Engine DIFFSERV Table Command Register (SWE_DIFFSERV_TBL_CFG)................................................................................. 325
13.3.3.13 Switch Engine DIFFSERV Table Write Data Register (SWE_DIFFSERV_TBL_WR_DATA) ...................................................................... 326
13.3.3.14 Switch Engine DIFFSERV Table Read Data Register (SWE_DIFFSERV_TBL_RD_DATA)....................................................................... 327
13.3.3.15 Switch Engine DIFFSERV Table Command Status Register (SWE_DIFFSERV_TBL_CMD_STS)............................................................ 328
13.3.3.16 Switch Engine Global Ingress Configuration Register (SWE_GLOBAL_INGRSS_CFG)............................................................................. 329
Revision 1.2 (04-08-08)
8
SMSC LAN9313/LAN9313i
DATASHEET
SMSC [ SMSC CORPORATION ]
