Three Port 10/100 Managed Ethernet Switch with MII
Datasheet
Chapter 5 System Interrupts
5.1
Functional Overview
This chapter describes the system interrupt structure of the LAN9313/LAN9313i. The
LAN9313/LAN9313i provides a multi-tier programmable interrupt structure which is controlled by the
System Interrupt Controller. The programmable system interrupts are generated internally by the
various LAN9313/LAN9313i sub-modules and can be configured to generate a single external host
interrupt via the IRQ interrupt output pin. The programmable nature of the host interrupt provides the
user with the ability to optimize performance dependent upon the application requirements. The IRQ
interrupt buffer type, polarity, and de-assertion interval are modifiable. The IRQ interrupt can be
configured as an open-drain output to facilitate the sharing of interrupts with other devices. All internal
interrupts are maskable and capable of triggering the IRQ interrupt.
5.2
Interrupt Sources
The LAN9313/LAN9313i is capable of generating the following interrupt types:
1588 Time Stamp Interrupts (Port 2,1,0 and GPIO 9,8)
Switch Fabric Interrupts (Buffer Manager, Switch Engine, and Port 2,1,0 MACs)
Ethernet PHY Interrupts (Port 1,2 PHYs)
GPIO Interrupts (GPIO[11:0])
General Purpose Timer Interrupt (GPT)
Software Interrupt (General Purpose)
Device Ready Interrupt
All interrupts are accessed and configured via registers arranged into a multi-tier, branch-like structure,
as shown in Figure 5.1. At the top level of the LAN9313/LAN9313i interrupt structure are the Interrupt
Status Register (INT_STS), Interrupt Enable Register (INT_EN), and Interrupt Configuration Register
(IRQ_CFG).
The Interrupt Status Register (INT_STS) and Interrupt Enable Register (INT_EN) aggregate and
enable/disable all interrupts from the various LAN9313/LAN9313i sub-modules, combining them
together to create the IRQ interrupt. These registers provide direct interrupt access/configuration to the
General Purpose Timer, software, and device ready interrupts. These interrupts can be monitored,
enabled/disabled, and cleared, directly within these two registers. In addition, interrupt event
indications are provided for the 1588 Time Stamp, Switch Fabric, Port 1 & 2 Ethernet PHYs, and GPIO
interrupts. These interrupts differ in that the interrupt sources are generated and cleared in other sub-
block registers. The INT_STS register does not provide details on what specific event within the sub-
module caused the interrupt, and requires the software to poll an additional sub-module interrupt
register (as shown in Figure 5.1) to determine the exact interrupt source and clear it. For interrupts
which involve multiple registers, only after the interrupt has been serviced and cleared at its source
will it be cleared in the INT_STS register.
The Interrupt Configuration Register (IRQ_CFG) is responsible for enabling/disabling the IRQ interrupt
output pin as well as configuring its properties. The IRQ_CFG register allows the modification of the
IRQ pin buffer type, polarity, and de-assertion interval. The de-assertion timer guarantees a minimum
interrupt de-assertion period for the IRQ output and is programmable via the INT_DEAS field of the
Interrupt Configuration Register (IRQ_CFG). A setting of all zeros disables the de-assertion timer. The
de-assertion interval starts when the IRQ pin de-asserts, regardless of the reason.
Revision 1.2 (04-08-08)
SMSC LAN9313/LAN9313i
DATA5S2HEET
SMSC [ SMSC CORPORATION ]
