Three Port 10/100 Managed Ethernet Switch with MII
Datasheet
emulated link partner. The default values of these bits are as shown in Section 13.1.7.5, "Virtual PHY
Auto-Negotiation Advertisement Register (VPHY_AN_ADV)," on page 216.
The symmetric/asymmetric pause ability of the emulated link partner is based upon the advertised
pause flow control abilities of the Virtual PHY in (bits 10 & 11) of the Virtual PHY Auto-Negotiation
Advertisement Register (VPHY_AN_ADV). Thus, the emulated link partner always accommodates the
asymmetric/symmetric pause ability settings requested by the Virtual PHY, as shown in Table 13.5,
“Emulated Link Partner Pause Flow Control Ability Default Values,” on page 219.
The pause flow control settings may also be manually set via the Port 0(External MII) Manual Flow
Control Register (MANUAL_FC_MII). This register allows the switch fabric port 0 flow control settings
to be manually set when auto-negotiation is disabled or the Manual Flow Control Select bit 0 is set.
The currently enabled duplex and flow control settings can also be monitored via this register. The flow
control values in the Virtual PHY Auto-Negotiation Advertisement Register (VPHY_AN_ADV) are not
affected by the values of the manual flow control register. Refer to Section 6.2.3, "Flow Control Enable
Logic," on page 60 for additional information.
7.3.2
Virtual PHY in MAC Modes
In the MAC modes of operation, an external PHY is connected to the MII interface of the
LAN9313/LAN9313i. Because there is an external PHY present, the Virtual PHY is not needed for
external configuration. However, the port 0 switch fabric MAC still requires the proper duplex setting.
Therefore, in MAC mode, if the auto-negotiation bit (VPHY_AN) of the Virtual PHY Basic Control
Register (VPHY_BASIC_CTRL) is set, the duplex is based on the MII_DUPLEX pin and
duplex_pol_strap_mii configuration strap. If these signals are equal, the port 0 switch fabric MAC is
configured for full-duplex, otherwise it is set for half-duplex. The MII_DUPLEX pin is typically connected
to the duplex indication of the external PHY. The duplex is not latched since the auto-negotiation
process is not used. The duplex can be manually selected by clearing the auto-negotiation bit
(VPHY_AN) and controlling the duplex mode (VPHY_DUPLEX) bit in the Virtual PHY Basic Control
Register (VPHY_BASIC_CTRL).
Note: In MAC modes, the Virtual PHY registers are accessible through their memory mapped
registers via the SMI, SPI, or I2C serial management interfaces only. The Virtual PHY registers
are not accessible through MII management.
7.3.2.1
Full-Duplex Flow Control
In the MAC modes of operation, the Virtual PHY is not applicable. Therefore, full-duplex flow control
should be controlled manually by the host via the Port 0(External MII) Manual Flow Control Register
(MANUAL_FC_MII), based on the external PHYs auto-negotiation results.
7.3.3
Virtual PHY Resets
In addition to the chip-level hardware reset (nRST) and Power-On Reset (POR), the Virtual PHY
supports two block specific resets. These are is discussed in the following sections. For detailed
information on all LAN9313/LAN9313i resets, refer to Section 4.2, "Resets," on page 41.
7.3.3.1
7.3.3.2
Virtual PHY Software Reset via RESET_CTL
The Virtual PHY can be reset via the Reset Control Register (RESET_CTL) by setting bit 3
(VPHY_RST). This bit is self clearing after approximately 102uS.
Virtual PHY Software Reset via VPHY_BASIC_CTRL
The Virtual PHY can also be reset by setting bit 15 (VPHY_RST) of the Virtual PHY Basic Control
Register (VPHY_BASIC_CTRL). This bit is self clearing and will return to 0 after the reset is complete.
Revision 1.2 (04-08-08)
100
SMSC LAN9313/LAN9313i
DATASHEET
SMSC [ SMSC CORPORATION ]
