欢迎访问ic37.com |
会员登录 免费注册
发布采购

LAN9217-MT-E2 参数 Datasheet PDF下载

LAN9217-MT-E2图片预览
型号: LAN9217-MT-E2
PDF下载: 下载PDF文件 查看货源
内容描述: 16位高性能单芯片10/100以太网控制器与HP Auto-MDIX的 [16-bit High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX]
分类和应用: 控制器以太网局域网(LAN)标准
文件页数/大小: 134 页 / 1591 K
品牌: SMSC [ SMSC CORPORATION ]
 浏览型号LAN9217-MT-E2的Datasheet PDF文件第46页浏览型号LAN9217-MT-E2的Datasheet PDF文件第47页浏览型号LAN9217-MT-E2的Datasheet PDF文件第48页浏览型号LAN9217-MT-E2的Datasheet PDF文件第49页浏览型号LAN9217-MT-E2的Datasheet PDF文件第51页浏览型号LAN9217-MT-E2的Datasheet PDF文件第52页浏览型号LAN9217-MT-E2的Datasheet PDF文件第53页浏览型号LAN9217-MT-E2的Datasheet PDF文件第54页  
16-bit High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX  
Datasheet  
BITS  
DESCRIPTION  
7
Reserved. This bit is reserved. Always write zeros to this field to guarantee future compatibility.  
6:3  
2
Collision Count. This counter indicates the number of collisions that occurred before the packet was  
transmitted. It is not valid when excessive collisions (bit 8) is also set.  
Excessive Deferral. If the deferred bit is set in the control register, the setting of the excessive  
deferral bit indicates that the transmission has ended because of a deferral of over 24288 bit times  
during transmission.  
1
Underrun Error. When set, this bit indicates that the transmitter aborted the associated frame  
because of an underrun condition of the TX data FIFO. TX Underrun will cause the assertion of the  
TXE error flag.  
0
Deferred. When set, this bit indicates that the current packet transmission was deferred.  
3.14.5  
Calculating Actual TX Data FIFO Usage  
The following rules are used to calculate the actual TX data FIFO space consumed by a TX Packet:  
„
„
TX command 'A' is stored in the TX data FIFO for every TX buffer  
TX command 'B' is written into the TX data FIFO when the First Segment (FS) bit is set in TX  
command 'A'  
„
Any DWORD-long data added as part of the “Data Start Offset” is removed from each buffer before  
the data is written to the TX data FIFO. Any data that is less than 1 DWORD is passed to the TX  
data FIFO.  
„
„
Payload from each buffer within a Packet is written into the TX data FIFO.  
Any DWORD-long data added as part of the End Padding is removed from each buffer before the  
data is written to the TX data FIFO. Any end padding that is less than 1 DWORD is passed to the  
TX data FIFO  
3.14.6  
Transmit Examples  
3.14.6.1  
TX Example 1  
In this example a single, 111-Byte Ethernet packet will be transmitted. This packet is divided into three  
buffers. The three buffers are as follows:  
Buffer 0:  
„
„
„
7-Byte “Data Start Offset”  
79-Bytes of payload data  
16-Byte “Buffer End Alignment”  
Buffer 1:  
„
„
„
0-Byte “Data Start Offset”  
15-Bytes of payload data  
16-Byte “Buffer End Alignment”  
Buffer 2:  
„
„
„
10-Byte “Data Start Offset”  
17-Bytes of payload data  
16-Byte “Buffer End Alignment”  
Revision 1.5 (07-18-06)  
SMSC LAN9217  
DATA5S0HEET