Highly Efficient Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support
Datasheet
In addition to the host-accessible FIFOs, the MAC Interface Layer (MIL) contains an additional 2K
bytes of TX, and 128 bytes of RX FIFO buffering. These sizes are fixed, and cannot be adjusted by
the host.
As space in the TX MIL (Mac Interface Layer) FIFO frees, data is moved into it from the TX data FIFO.
Depending on the size of the frames to be transmitted, the MIL can hold up to two Ethernet frames.
This is in addition to any TX data that may be queued in the TX data FIFO.
Conversely, as data is received by the LAN9215i, it is moved from the MAC to the RX MIL FIFO, and
then into the RX data FIFO. When the RX data FIFO fills up, data will continue to collect in the RX
MIL FIFO. If the RX MIL FIFO fills up and overruns, subsequent RX frames will be lost until room is
made in the RX data FIFO. For each frame of data that is lost, the RX Dropped Frames Counter
(RX_DROP) is incremented.
RX and TX MIL FIFO levels are not visible to the host processor. RX and TX MIL FIFOs operate
independent of the TX data and RX data and status FIFOs. FIFO levels set for the RX and TX data
and Status FIFOs do not take into consideration the MIL FIFOs.
5.3.10
RX_DP_CTRL—Receive Datapath Control Register
Offset:
78h
Size:
32 bits
This register is used to discard unwanted receive frames.
BITS
DESCRIPTION
TYPE
DEFAULT
31
RX Data FIFO Fast Forward (RX_FFWD): Writing a ‘1’ to this bit causes
the RX data FIFO to fast-forward to the start of the next frame. This bit will
remain high until the RX data FIFO fast-forward operation has completed.
No reads should be issued to the RX data FIFO while this bit is high.
R/W
SC
0b
Note:
Please refer to section “Receive Data FIFO Fast Forward” on
page 57 for detailed information regarding the use of RX_FFWD.
30-0
Reserved
RO
-
Revision 1.93 (12-12-07)
86
SMSC LAN9215i
DATASHEET
SMSC [ SMSC CORPORATION ]
