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LAN9215I-MT 参数 Datasheet PDF下载

LAN9215I-MT图片预览
型号: LAN9215I-MT
PDF下载: 下载PDF文件 查看货源
内容描述: 高效的单芯片10/100以太网控制器与HP Auto-MDIX的和工业温度支持 [Highly Efficient Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support]
分类和应用: 外围集成电路数据传输控制器局域网以太网局域网(LAN)标准时钟
文件页数/大小: 134 页 / 1602 K
品牌: SMSC [ SMSC CORPORATION ]
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Highly Efficient Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support  
Datasheet  
The MAC Interface Layer (MIL), within the MAC, contains a 2K Byte transmit and a 128 Byte receive  
FIFO which is separate from the TX and RX FIFOs. The FIFOs within the MAC are not directly  
accessible from the host interface. The differentiation between the TX/RX FIFO memory buffers and  
the MAC buffers is that when the transmit or receive packets are in the MAC buffers, the host no longer  
can control or access the TX or RX data. The MAC buffers (both TX and RX) are in effect the working  
buffers of the Ethernet MAC logic. In the case of reception, the data must be moved first to the RX  
FIFOs for the host to access the data.  
1.5  
Receive and Transmit FIFOs  
The Receive and Transmit FIFOs allow increased packet buffer storage to the MAC. The FIFOs are a  
conduit between the host interface and the MAC through which all transmitted and received data and  
status information is passed. Deep FIFOs allow a high degree of latency tolerance relative to the  
various transport and OS software stacks thus reducing or minimizing overrun conditions. Like the  
MAC, the FIFOs have separate receive and transmit data paths. In addition, the RX and TX FIFOs are  
configurable in size, allowing increased flexibility.  
1.6  
1.7  
Interrupt Controller  
The LAN9215I supports a single programmable interrupt. The programmable nature of this interrupt  
allows the user the ability to optimize performance dependent upon the application requirement. Both  
the polarity and buffer type of the interrupt pin are configurable for the external interrupt processing.  
The interrupt line can be configured as an open-drain output to facilitate the sharing of interrupts with  
other devices. In addition, a programmable interrupt de-assertion interval is provided.  
GPIO Interface  
A 3-bit GPIO and 2-bit GPO (Multiplexed on the EEPROM and LED Pins) interface is included in the  
LAN9215I. It is accessible through the host bus interface via the CSRs. The GPIO signals can function  
as inputs, push-pull outputs and open drain outputs. The GPIO’s (GPO’s are not configurable) can also  
be configured to trigger interrupts with programmable polarity.  
1.8  
1.9  
Serial EEPROM Interface  
A serial EEPROM interface is included in the LAN9215I. The serial EEPROM is optional and can be  
programmed with the LAN9215I MAC address. The LAN9215I can optionally load the MAC address  
automatically after power-on.  
Power Management Controls  
The LAN9215I supports comprehensive array of power management modes to allow use in power  
sensitive applications. Wake on LAN, Link Status Change and Magic Packet detection are supported  
by the LAN9215I. An external PME (Power Management Event) interrupt is provided to indicate  
detection of a wakeup event.  
1.10  
General Purpose Timer  
The general-purpose timer has no dedicated function within the LAN9215I and may be programmed  
to issue a timed interrupt.  
Revision 1.5 (07-18-06)  
SMSC LAN9215I  
DATA1S2HEET  
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