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LAN9215I-MT 参数 Datasheet PDF下载

LAN9215I-MT图片预览
型号: LAN9215I-MT
PDF下载: 下载PDF文件 查看货源
内容描述: 高效的单芯片10/100以太网控制器与HP Auto-MDIX的和工业温度支持 [Highly Efficient Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support]
分类和应用: 外围集成电路数据传输控制器局域网以太网局域网(LAN)标准时钟
文件页数/大小: 134 页 / 1602 K
品牌: SMSC [ SMSC CORPORATION ]
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Highly Efficient Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support  
Datasheet  
1.2  
Internal Block Overview  
This section provides an overview of each of these functional blocks as shown in Figure 1.2, "Internal  
Block Diagram".  
25MHz  
EEPROM  
(Optional)  
+3.3V  
EEPROM  
Controller  
3.3V to 1.8V  
Regulator  
PLL  
PME - Wakup Indicator  
Power Management  
2kB to 14kB  
Configurable TX FIFO  
Host Bus Interface  
(HBI)  
10/100  
Ethernet  
PHY  
LAN  
16-bit SRAM I/F  
TX Status FIFO  
RX Status FIFO  
10/100  
Ethernet  
PIO Controller  
MAC  
IRQ  
Interrupt  
Controller  
MIL - RX Elastic  
Buffer - 128 bytes  
Optional  
FIFO_SEL  
2kB to 14kB  
Configurable RX FIFO  
External PHY - MII  
Interface  
MIL - TX Elastic  
Buffer - 2K bytes  
GP Timer  
Figure 1.2 Internal Block Diagram  
1.3  
1.4  
10/100 Ethernet PHY  
The LAN9215I integrates an IEEE 802.3 physical layer for twisted pair Ethernet applications. The PHY  
can be configured for either 100 Mbps (100Base-TX) or 10 Mbps (10Base-T) Ethernet operation in  
either full or half duplex configurations. The PHY block supports HP Auto-MDIX and auto-negotiation.  
Minimal external components are required for the utilization of the Integrated PHY.  
10/100 Ethernet MAC  
The transmit and receive data paths are separate within the MAC allowing the highest performance  
especially in full duplex mode. The data paths connect to the PIO interface Function via separate  
busses to increase performance. Payload data as well as transmit and receive status is passed on  
these busses.  
A third internal bus is used to access the MAC’s Control and Status Registers (CSR’s). This bus is  
accessible from the host through the PIO interface function.  
On the backend, the MAC interfaces with the internal 10/100 PHY through a the MII (Media  
Independent Interface) port internal to the LAN9215I. The MAC CSR's also provides a mechanism for  
accessing the PHY’s internal registers through the internal SMI (Serial Management Interface) bus.  
The Ethernet MAC can also communicate with an external PHY. This mode however, is optional.  
SMSC LAN9215I  
11  
Revision 1.5 (07-18-06)  
DATASHEET  
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