High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX
Datasheet
Note: CSR and status FIFO accesses are not affected by the FPORTEND and FSELEND endianess
select bits.
3.7.4
Word Swap Function
In addition to mixed endian functionality, the LAN9211 supports a Word Swap Function. This feature
is controlled by the Word Swap Register, which is described in Section 5.3.17, "WORD_SWAP—Word
Swap Control," on page 98. This register affects how words on the data bus are written to or read from
the Control and Status Registers and the Transmit and Receive Data/Status FIFOs.
Both the word swap function and the mixed endian control bits contain the ability to change the byte
ordering of host data path accesses. Figure 3.2 illustrates the order in which the word swap and
endianess select logic is applied within the LAN9211. Logically, the endian control logic is applied after
the word swap logic for write operations, and before the word swap logic for read operations.
RX/TX Data FIFO Port
Access (addresses 00h to
3Ch)
RX/TX Data FIFO Direct
Access
CSRs and Status FIFOs
(FIFO_SEL = 1)
FIFO Port Endian Ordering
Logic
Direct FIFO Access Endian
Ordering Logic
FSELEND
(HW_CFG[28])
FPORTEND
(HW_CFG[29])
"WORD SWAP"
Logic
WORD_SWAP
D[15:0]
(Host Data Bus)
Figure 3.2 LAN9211 Host Data Path Diagram
Data path operations for the various supported endianess and word swap configurations are illustrated
in Figure 3.3. Table 3.8, "Endian Ordering Logic Operation" illustrates the byte ordering applied by the
endian logic for each type of host access. This figure and table assume an internal byte ordering of 3-
2-1-0, where ‘3’ is the most significant byte (data[31:24]) and ‘0’ is the least significant byte (data[7:0]).
Revision 1.93 (11-27-07)
34
SMSC LAN9211
DATASHEET
SMSC [ SMSC CORPORATION ]
