High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
Table 7.2 4B/5B Code Table
CODE
GROUP
RECEIVER
INTERPRETATION
TRANSMITTER
INTERPRETATION
SYM
11110
01001
10100
10101
01010
01011
01110
01111
10010
10011
10110
10111
11010
11011
11100
11101
11111
0
1
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
DATA
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
DATA
2
3
4
5
6
7
8
9
A
B
C
D
E
F
/I/
IDLE
Sent after /T/R/ until the MII Transmitter
Enable signal (TXEN) is received
11000
10001
01101
00111
/J/
/K/
/T/
/R/
First nibble of SSD, translated to “0101”
following IDLE, else MII Receive Error
(RXER)
Sent for rising MII Transmitter Enable
signal (TXEN)
Second nibble of SSD, translated to
“0101” following J, else MII Receive
Error (RXER)
Sent for rising MII Transmitter Enable
signal (TXEN)
First nibble of ESD, causes de-assertion
of CRS if followed by /R/, else assertion
of MII Receive Error (RXER)
Sent for falling MII Transmitter Enable
signal (TXEN)
Second nibble of ESD, causes de-
assertion of CRS if following /T/, else
assertion of MII Receive Error (RXER)
Sent for falling MII Transmitter Enable
signal (TXEN)
00100
00110
/H/
/V/
Transmit Error Symbol
Sent for rising MII Transmit Error (TXER)
INVALID
INVALID, MII Receive Error (RXER) if
during MII Receive Data Valid (RXDV)
11001
00000
00001
/V/
/V/
/V/
INVALID, MII Receive Error (RXER) if
during MII Receive Data Valid (RXDV)
INVALID
INVALID
INVALID
INVALID, MII Receive Error (RXER) if
during MII Receive Data Valid (RXDV)
INVALID, MII Receive Error (RXER) if
during MII Receive Data Valid (RXDV)
SMSC LAN9312
Revision 1.2 (04-08-08)
DATA8S5HEET
SMSC [ SMSC CORPORATION ]
