High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
6.5.7
Counters
A counter is maintained per port that contains the number of packets dropped due to buffer space limits
and ingress rate limit discarding (Red and random Yellow dropping). These counters are accessible
via the following registers:
Buffer Manager Port 0 Drop Count Register (BM_DRP_CNT_SRC_MII)
Buffer Manager Port 1 Drop Count Register (BM_DRP_CNT_SRC_1)
Buffer Manager Port 2 Drop Count Register (BM_DRP_CNT_SRC_2)
A counter is maintained per port that contains the number of packets dropped due solely to ingress
rate limit discarding (Red and random Yellow dropping). This count value can be subtracted from the
drop counter, as described above, to obtain the drop counts due solely to buffer space limits. The
ingress rate drop counters are accessible via the following registers:
Buffer Manager Port 0 Ingress Rate Drop Count Register (BM_RATE_DRP_CNT_SRC_MII)
Buffer Manager Port 1 Ingress Rate Drop Count Register (BM_RATE_DRP_CNT_SRC_1)
Buffer Manager Port 2 Ingress Rate Drop Count Register (BM_RATE_DRP_CNT_SRC_2)
6.6
Switch Fabric Interrupts
The switch fabric is capable of generating multiple maskable interrupts from the buffer manager, switch
engine, and MACs. These interrupts are detailed in Section 5.2.2, "Switch Fabric Interrupts," on
page 51.
SMSC LAN9312
Revision 1.2 (04-08-08)
DATA8S1HEET
SMSC [ SMSC CORPORATION ]
