High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
register. When Auto-negotiation is enabled and the MANUAL_FC_x bit is cleared, the switch port flow
control enables during full-duplex are determined by Auto-negotiation.
Note: The flow control values in the Port x PHY Auto-Negotiation Advertisement Register
(PHY_AN_ADV_x) and Virtual PHY Auto-Negotiation Advertisement Register
(VPHY_AN_ADV) are not affected by the values of the manual flow control register. Refer to
Section 7.2.5.1, "PHY Pause Flow Control," on page 92 and Section 7.3.1.3, "Virtual PHY
Pause Flow Control," on page 98 for additional information on PHY and Virtual PHY flow
control settings respectively.
Table 6.1 Switch Fabric Flow Control Enable Logic
BP_EN_x
-
-
1
X
1
X
0
0
0
0
0
0
0
0
0
0
0
X
0
X
0
1
1
1
1
1
1
1
1
1
1
1
X
X
X
X
0
1
1
1
1
1
1
1
1
1
1
X
X
X
X
X
0
1
1
1
1
1
1
1
1
1
Half
Half
X
X
X
X
X
X
X
0
0
0
0
1
1
1
1
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
0
0
BP_EN_x
TX_FC_x
TX_FC_x
0
RX_FC_x
-
Full
RX_FC_x
-
Full
1
2
3
4
5
6
7
8
9
10
11
X
0
0
0
0
0
0
0
0
1
0
1
0
BP_EN_x
Half (Note 6.1)
Half
BP_EN_x
Full
0
0
0
1
0
1
0
0
Full
1
Full
1
1
Full
1
1
1
Full
0
0
X
X
0
Full
X
1
1
Full
0
Full
1
0
1
Note 6.1 If Auto-negotiation is enabled and complete, but the link partner is not Auto-negotiation
capable, half-duplex is forced via the parallel detect function.
Note 6.2 For the Port 1 and Port 2 PHYs, these are the bits from the Port x PHY Auto-Negotiation
Advertisement Register (PHY_AN_ADV_x) and Port x PHY Auto-Negotiation Link Partner
Base Page Ability Register (PHY_AN_LP_BASE_ABILITY_x). For the Virtual PHY, these
are the local/partner swapped outputs from the bits in the Virtual PHY Auto-Negotiation
Advertisement Register (VPHY_AN_ADV) and Virtual PHY Auto-Negotiation Link Partner
Base Page Ability Register (VPHY_AN_LP_BASE_ABILITY). Refer to Section 7.3.1,
"Virtual PHY Auto-Negotiation," on page 96 for more information.
SMSC LAN9312
Revision 1.2 (04-08-08)
DATA5S9HEET