High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
6.2.1
Switch Fabric CSR Writes
To perform a write to an individual switch fabric register, the desired data must first be written into the
Switch Fabric CSR Interface Data Register (SWITCH_CSR_DATA). The write cycle is initiated by
performing a single write to the Switch Fabric CSR Interface Command Register
(SWITCH_CSR_CMD) with CSR_BUSY (bit 31) set, the CSR_ADDRESS field (bits 15:0) set to the
desired register address, the R_nW (bit 30) cleared, the AUTO_INC and AUTO_DEC fields cleared,
and the desired CSR byte enable bits selected (bits 19:16). The completion of the write cycle is
indicated by the clearing of the CSR_BUSY bit.
A second write method may be used which utilizes the auto increment/decrement function of the
Switch Fabric CSR Interface Command Register (SWITCH_CSR_CMD) for writing sequential register
addresses. When using this method, the Switch Fabric CSR Interface Command Register
(SWITCH_CSR_CMD) must first be written with the auto increment(AUTO_INC) or auto
decrement(AUTO_DEC) bit set, the CSR_ADDRESS field written with the desired register address, the
R_nW bit cleared, and the desired CSR byte enable bits selected (typically all set). The write cycles
are then initiated by writing the desired data into the Switch Fabric CSR Interface Data Register
(SWITCH_CSR_DATA). The completion of the write cycle is indicated by the clearing of the
CSR_BUSY bit, at which time the address in the Switch Fabric CSR Interface Command Register
(SWITCH_CSR_CMD) is incremented or decremented accordingly. The user may then initiate a
subsequent write cycle by writing the desired data into the Switch Fabric CSR Interface Data Register
(SWITCH_CSR_DATA).
The third write method is to use the direct data range write function. Writes within the Switch Fabric
CSR Interface Direct Data Register (SWITCH_CSR_DIRECT_DATA) address range automatically set
the appropriate register address, set all four byte enable bits (CSR_BE[3:0]), clears the R_nW bit, and
sets the CSR_BUSY bit of the Switch Fabric CSR Interface Command Register
(SWITCH_CSR_CMD). The completion of the write cycle is indicated by the clearing of the
CSR_BUSY bit. Since the address range of the switch fabric CSRs exceeds that of the Switch Fabric
CSR Interface Direct Data Register (SWITCH_CSR_DIRECT_DATA) address range, a sub-set of the
switch fabric CSRs are mapped to the Switch Fabric CSR Interface Direct Data Register
(SWITCH_CSR_DIRECT_DATA) address range as detailed in Table 14.3, “Switch Fabric CSR to
SWITCH_CSR_DIRECT_DATA Address Range Map,” on page 240.
Figure 6.1 illustrates the process required to perform a switch fabric CSR write. The minimum wait
periods as specified in Table 8.1, “Read After Write Timing Rules,” on page 101 are required where
noted.
Revision 1.2 (04-08-08)
SMSC LAN9312
DATA5S6HEET
SMSC [ SMSC CORPORATION ]
