High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
14.5.3.39 Switch Engine Interrupt Mask Register (SWE_IMR)
Register #:
1880h
Size:
32 bits
This register contains the Switch Engine interrupt mask, which masks the interrupts in the Switch
Engine Interrupt Pending Register (SWE_IPR). All Switch Engine interrupts are masked by setting the
Interrupt Mask bit. Clearing this bit will unmask the interrupts. Refer to Chapter 5, "System Interrupts,"
on page 49 for more information.
BITS
DESCRIPTION
TYPE
DEFAULT
31:1
0
RESERVED
RO
-
Interrupt Mask
R/W
1b
When set, this bit masks interrupts from the Switch Engine. The status bits
in the Switch Engine Interrupt Pending Register (SWE_IPR) are not
affected.
SMSC LAN9312
409
Revision 1.2 (04-08-08)
DATASHEET
SMSC [ SMSC CORPORATION ]
