High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
14.5.3.21 Switch Engine Port Mirroring Register (SWE_PORT_MIRROR)
Register #:
1846h
Size:
32 bits
This register is used to configure port mirroring.
BITS
DESCRIPTION
TYPE
DEFAULT
31:9
8
RESERVED
RO
-
Enable RX Mirroring Filtered
R/W
0b
When set, packets that would normally have been filtered are included in the
receive mirroring function and are sent only to the sniffer port. When
cleared, filtered packets are not mirrored.
Note:
The Ingress Filtered Count Registers will still count these packets
as filtered and the Switch Engine Interrupt Pending Register
(SWE_IPR) will still register a drop interrupt.
7:5
4:2
Sniffer Port
R/W
R/W
00b
00b
These bits specify the sniffer port that transmits packets that are monitored.
Bits 7,6,5 correspond to switch ports 2,1,0 respectively.
Note:
Only one port should be set as the sniffer.
Mirrored Port
These bits specify if a port is to be mirrored. Bits 4,3,2 correspond to switch
ports 2,1,0 respectively.
Note:
Multiple ports can be set as mirrored.
1
0
Enable RX Mirroring
R/W
R/W
0b
0b
This bit enables packets received on the mirrored ports to be also sent to
the sniffer port.
Enable TX Mirroring
This bit enables packets transmitted on the mirrored ports to be also sent to
the sniffer port.
Revision 1.2 (04-08-08)
390
SMSC LAN9312
DATASHEET
SMSC [ SMSC CORPORATION ]
