High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
14.5.3.20 Switch Engine Priority to Queue Register (SWE_PRI_TO_QUE)
Register #:
1845h
Size:
32 bits
This register specifies the Traffic Class table that maps the packet priority into the egress queues.
BITS
DESCRIPTION
TYPE
DEFAULT
31:16
15:14
RESERVED
RO
-
Priority 7 traffic Class
These bits specify the egress queue that is used for packets with a priority
of 7.
R/W
11b
13:12
11:10
9:8
Priority 6 traffic Class
R/W
R/W
R/W
R/W
R/W
R/W
R/W
11b
10b
10b
01b
00b
00b
01b
These bits specify the egress queue that is used for packets with a priority
of 6.
Priority 5 traffic Class
These bits specify the egress queue that is used for packets with a priority
of 5.
Priority 4 traffic Class
These bits specify the egress queue that is used for packets with a priority
of 4.
7:6
Priority 3 traffic Class
These bits specify the egress queue that is used for packets with a priority
of 3.
5:4
Priority 2 traffic Class
These bits specify the egress queue that is used for packets with a priority
of 2.
3:2
Priority 1 traffic Class
These bits specify the egress queue that is used for packets with a priority
of 1.
1:0
Priority 0 traffic Class
These bits specify the egress queue that is used for packets with a priority
of 0.
SMSC LAN9312
389
Revision 1.2 (04-08-08)
DATASHEET
SMSC [ SMSC CORPORATION ]
