High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
14.5.3.12 Switch Engine DIFFSERV Table Command Register (SWE_DIFFSERV_TBL_CFG)
Register #:
1811h
Size:
32 bits
This register is used to read and write the DIFFSERV table. A write to this address performs the
specified access. This table is used to map the received IP ToS/CS to a priority.
For a read access, the Operation Pending bit in the Switch Engine DIFFSERV Table Command Status
Register (SWE_DIFFSERV_TBL_CMD_STS) indicates when the command is finished. The Switch
Engine DIFFSERV Table Read Data Register (SWE_DIFFSERV_TBL_RD_DATA) can then be read.
For a write access, the Switch Engine DIFFSERV Table Write Data Register
(SWE_DIFFSERV_TBL_WR_DATA) register should be written first. The Operation Pending bit in the
Switch Engine DIFFSERV Table Command Status Register (SWE_DIFFSERV_TBL_CMD_STS)
indicates when the command is finished.
BITS
DESCRIPTION
TYPE
DEFAULT
31:8
7
RESERVED
RO
-
DIFFSERV Table RnW
This bit specifies a read(1) or a write(0) command.
R/W
0b
6
RESERVED
RO
-
5:0
DIFFSERV Table Index
This field specifies the ToS/CS entry that is accessed.
R/W
0h
Revision 1.2 (04-08-08)
380
SMSC LAN9312
DATASHEET
SMSC [ SMSC CORPORATION ]
