High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
14.5.3.6
Switch Engine ALR Command Status Register (SWE_ALR_CMD_STS)
Register #:
1808h
Size:
32 bits
This register indicates the current ALR command status.
BITS
DESCRIPTION
TYPE
DEFAULT
31:2
1
RESERVED
RO
-
ALR Init Done
RO
SS
Note 14.62
When set, indicates that the ALR table has finished being initialized by the
reset process. The initialization is performed upon any reset that resets the
switch fabric. The initialization takes approximately 20uS. During this time,
any received packet will be dropped. Software should monitor this bit before
writing any of the ALR tables or registers.
0
Make Pending
RO
SC
0b
When set, indicates that the Make Entry command is taking place. This bit
is cleared once the Make Entry command has finished.
Note 14.62 The default value of this bit is 0 immediately following any switch fabric reset and then self-
sets to 1 once the ALR table is initialized.
Revision 1.2 (04-08-08)
374
SMSC LAN9312
DATASHEET
SMSC [ SMSC CORPORATION ]
