High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
14.5.2.44 Port x MAC Interrupt Pending Register (MAC_IPR_x)
Register #:
Port0: 0481h
Port1: 0881h
Port2: 0C81h
Size:
32 bits
This read-only register contains the pending Port x interrupts. A set bit indicates an interrupt has been
triggered. All interrupts in this register may be masked via the Port x MAC Interrupt Pending Register
(MAC_IPR_x) register. Refer to Chapter 5, "System Interrupts," on page 49 for more information.
Note: There are no possible Port x interrupt conditions available. This register exists for future use.
BITS
DESCRIPTION
TYPE
DEFAULT
31:0
RESERVED
RO
-
Revision 1.2 (04-08-08)
366
SMSC LAN9312
DATASHEET
SMSC [ SMSC CORPORATION ]
