High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
14.5.2.43 Port x MAC Interrupt Mask Register (MAC_IMR_x)
Register #:
Port0: 0480h
Port1: 0880h
Port2: 0C80h
Size:
32 bits
This register contains the Port x interrupt mask. Port x related interrupts in the Port x MAC Interrupt
Pending Register (MAC_IPR_x) may be masked via this register. An interrupt is masked by setting the
corresponding bit of this register. Clearing a bit will unmask the interrupt. Refer to Chapter 5, "System
Interrupts," on page 49 for more information.
Note: There are no possible Port x interrupt conditions available. This register exists for future use,
and should be configured as indicated for future compatibility.
BITS
DESCRIPTION
TYPE
DEFAULT
31:8
7:0
RESERVED
RESERVED
RO
-
R/W
11h
Note:
These bits must be written as 11h
SMSC LAN9312
365
Revision 1.2 (04-08-08)
DATASHEET
SMSC [ SMSC CORPORATION ]
