High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
Table 14.7 Port 1 & 2 PHY MII Serially Adressable Registers (continued)
INDEX #
SYMBOL
REGISTER NAME
PHY_MODE_CONTROL_STATUS_x
17
18
27
Port x PHY Mode Control/Status Register, Section 14.4.2.8
Port x PHY Special Modes Register, Section 14.4.2.9
PHY_SPECIAL_MODES_x
PHY_SPECIAL_CONTROL_STAT_IND_x
Port x PHY Special Control/Status Indication Register,
Section 14.4.2.10
PHY_INTERRUPT_SOURCE_x
29
30
31
Port x PHY Interrupt Source Flags Register, Section 14.4.2.11
Port x PHY Interrupt Mask Register, Section 14.4.2.12
Port x PHY Special Control/Status Register, Section 14.4.2.13
PHY_INTERRUPT_MASK_x
PHY_SPECIAL_CONTROL_STATUS_x
SMSC LAN9312
287
Revision 1.2 (04-08-08)
DATASHEET
SMSC [ SMSC CORPORATION ]
