High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
14.3
Host MAC Control and Status Registers
This section details the Host MAC System CSR’s. These registers are located in the Host MAC and
are accessed indirectly via the HBI system CSR’s. Table 14.6 lists Host MAC registers that are
accessible through the indexing method using the Host MAC CSR Interface Command Register
(MAC_CSR_CMD) and Host MAC CSR Interface Data Register (MAC_CSR_DATA).
The Host MAC registers allow configuration of the various Host MAC parameters including the Host
MAC address, flow control, multicast hash table, and wake-up configuration. The Host MAC CSR’s
also provide serial access to the PHYs via the registers HMAC_MII_ACC and HMAC_MII_DATA.
These registers allow access to the 10/100 Ethernet PHY registers and the switch engine (via Port 0).
Table 14.6 Host MAC Adressable Registers
INDEX #
SYMBOL
REGISTER NAME
Reserved for Future Use
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
RESERVED
HMAC_CR
Host MAC Control Register, Section 14.3.1
HMAC_ADDRH
HMAC_ADDRL
HMAC_HASHH
HMAC_HASHL
HMAC_MII_ACC
HMAC_MII_DATA
HMAC_FLOW
HMAC_VLAN1
HMAC_VLAN2
HMAC_WUFF
HMAC_WUCSR
Host MAC Address High Register, Section 14.3.2
Host MAC Address Low Register, Section 14.3.3
Host MAC Multicast Hash Table High Register, Section 14.3.4
Host MAC Multicast Hash Table Low Register, Section 14.3.5
Host MAC MII Access Register, Section 14.3.6
Host MAC MII Data Register, Section 14.3.7
Host MAC Flow Control Register, Section 14.3.8
Host MAC VLAN1 Tag Register, Section 14.3.9
Host MAC VLAN2 Tag Register, Section 14.3.10
Host MAC Wake-up Frame Filter Register, Section 14.3.11
Host MAC Wake-up Control and Status Register,
Section 14.3.12
0Dh-FFh
RESERVED
Reserved for Future Use
Revision 1.2 (04-08-08)
270
SMSC LAN9312
DATASHEET
SMSC [ SMSC CORPORATION ]
