High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
14.2.5.17 1588 Clock Target Low-DWORD Register (1588_CLOCK_TARGET_LO)
Offset:
180h
Size:
32 bits
This read/write register combined with 1588 Clock Target High-DWORD Register
(1588_CLOCK_TARGET_HI) form the 64-bit 1588 Clock Target value. The 1588 Clock Target value is
compared to the current 1588 Clock value and can be used to trigger an interrupt upon at match. Refer
to Chapter 11, "IEEE 1588 Hardware Time Stamp Unit," on page 154 for additional information.
BITS
DESCRIPTION
TYPE
DEFAULT
31:0
Clock Target Low (CLOCK_TARGET_LO)
This field contains the low 32-bits of the 64-bit 1588 Clock Compare value.
R/W
00000000h
Note: Both
this
register
and
the
1588
Clock
Target
High-DWORD
Register
(1588_CLOCK_TARGET_HI) must be written for either to be affected.
SMSC LAN9312
217
Revision 1.2 (04-08-08)
DATASHEET
SMSC [ SMSC CORPORATION ]
