High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
14.2.5.19
1588 Clock Target Reload/Add Low-DWORD Register (1588_CLOCK_TARGET_RELOAD_LO)
Offset:
188h
Size:
32 bits
This read/write register combined with 1588 Clock Target Reload High-DWORD Register
(1588_CLOCK_TARGET_RELOAD_HI) form the 64-bit 1588 Clock Target Reload value. The 1588
Clock Target Reload is the value that is reloaded or added to the 1588 Clock Compare value when a
clock compare event occurs. Whether this value is reloaded or added is determined by the Reload/Add
(RELOAD_ADD) bit of the 1588 Configuration Register (1588_CONFIG). Refer to Chapter 11, "IEEE
1588 Hardware Time Stamp Unit," on page 154 for additional information.
BITS
DESCRIPTION
TYPE
DEFAULT
31:0
Clock Target Reload Low (CLOCK_TARGET_RELOAD_LO)
This field contains the low 32-bits of the 64-bit 1588 Clock Target Reload
value that is reloaded to the 1588 Clock Compare value. Alternatively, these
32-bits are added to the 1588 Clock Compare value when configured
accordingly.
R/W
00000000h
Note: Both this register and the 1588 Clock Target Reload High-DWORD Register
(1588_CLOCK_TARGET_RELOAD_HI) must be written for either to be affected.
SMSC LAN9312
219
Revision 1.2 (04-08-08)
DATASHEET
SMSC [ SMSC CORPORATION ]
