High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
DIGITAL_RST, nRST,
POR, RELOAD
EPC_BUSY = 1
Read Byte 0
Load PHY registers with
current straps
N
Byte 0 = A5h
Y
Read Bytes 1-6
EPC_BUSY = 0
Write Bytes 1-6 into Host
MAC and switch MAC
Address Registers
N
Soft Reset
Y
Read Byte 7-11
EPC_BUSY = 1
Read Byte 0
Load PHY registers with
current straps
N
Byte 7 = A5h
Y
N
Byte 0 = A5h
Write Bytes 8-11 into
Configuration Strap
registers
Y
Read Bytes 1-6
Write Bytes 1-6 into Host
MAC Address Registers
Update PHY registers
Update VPHY registers
Update LED_CFG,
MANUAL_FC_1,
MANUAL_FC_2 and
MANUAL_FC_mii
registers
Read Byte 12
N
Byte 12 = A5h
Y
Perform register data
load loop
Figure 10.14 EEPROM Loader Flow Diagram
Revision 1.2 (04-08-08)
150
SMSC LAN9312
DATASHEET
SMSC [ SMSC CORPORATION ]
