High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
9.8.7
TX Data FIFO Underrun
If the Host MAC Interface Layer is not operating in store and forward mode, and the host is unable
supply data at the Ethernet line rate, the TX Data FIFO can underrun. If a TX underrun occurs, any
further data written to the TX Data FIFO for the offending frame (the frame being transmitted during
the underrun) will automatically be discarded and no further data for that frame will be transmitted. TX
Data FIFO underrun is not an error condition, and data transmission will resume with the next valid TX
command. In the case of a TX Data FIFO underrun, the (TDFU) flag is set in the Interrupt Status
Register (INT_STS) and can be used to generate a host interrupt. A TX Data FIFO underrun is also
indicated in the TX status word for the underrun frame.
In the case of a TX underrun, the host is still required to write the remainder of the current TX packet
to the LAN9312. Any remaining data from the underrun frame that is written to the LAN9312 will back-
up in the TX Data FIFO (no more data is read until the next TX SOF [start of frame]). As the data
backs up in the TX Data FIFO, it will be visible in the TX FIFO Information Register (TX_FIFO_INF).
In typical driver usage, software will write the entire transmit packet to the LAN9312 and check the
Interrupt Status Register (INT_STS) to see if an underrun has occurred (from the TDFU bit status).
Eventually, the driver will recognize the underrun. A '1' must then be written to the TXD_DUMP bit in
the Transmit Configuration Register (TX_CFG) to flush the remaining data in the TX Data FIFO (note
that TX_ON may be kept on while flushing the remaining TX Data FIFO contents). Once the leftover
data from the underrun frame is purged, the LAN9312 is ready to send new transmit packets. It is
advisable to clear the TDFU bit prior to transmitting any more data (assuming that SF=0) so that
subsequent underruns can be detected, but this is not required by the hardware.
9.8.8
Transmitter Errors
If the Transmitter Error (TXE) flag is asserted for any reason, the transmitter will continue operation.
TX Error (TXE) will be asserted under the following conditions:
If the actual packet length count does not match the Packet Length field as defined in the TX
command.
Both TX command ‘A’ and TX command ‘B’ are required for each buffer in a given packet. TX
command ‘B’ must be identical for every buffer in a given packet. If the TX command ‘B’ words do
not match, the Ethernet controller will assert the Transmitter Error (TXE) flag.
Host overrun of the TX Data FIFO.
Overrun of the TX Status FIFO (unless TXSAO is enabled)
9.8.9
Stopping and Starting the Transmitter
To halt the transmitter, the host must set the STOP_TX bit in the Transmit Configuration Register
(TX_CFG). The transmitter will finish sending the current frame (if there is a frame transmission in
progress). When the transmitter has received the TX status for this frame, it will clear the STOP_TX
and TX_ON bits, and will pulse the TXSTOP_INT in the Interrupt Status Register (INT_STS).
Once stopped, the host can optionally clear the TX Status and TX Data FIFOs. The host must re-
enable the transmitter by setting the TX_ON bit. If the there are frames pending in the TX Data FIFO
(i.e., TX Data FIFO was not purged), the transmission will resume with this data.
SMSC LAN9312
131
Revision 1.2 (04-08-08)
DATASHEET
SMSC [ SMSC CORPORATION ]
