FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications
In this case, the transmit interrupt service routine can find the next packet number to be serviced by reading the TX
FIFO PACKET NUMBER at the FIFO PORTS register. This eliminates the need for the driver to keep a list of packet
numbers being transmitted. The numbers are queued by the LAN91C110 and provided back to the CPU as their
transmission completes.
2. One interrupt per sequence of packets: Enable TX EMPTY INT and TX INT, set AUTO RELEASE=1. TX EMPTY
INT is generated only after transmitting the last packet in the FIFO.
TX INT will be set on a fatal transmit error allowing the CPU to know that the transmit process has stopped and
therefore the FIFO will not be emptied.
This mode has the advantage of a smaller CPU overhead, and faster memory de-allocation. Note that when AUTO
RELEASE=1 the CPU is not provided with the packet numbers that completed successfully.
Note: The pointer register is shared by any process accessing the LAN91C110 memory. In order to allow processes
to be interruptable, the interrupting process is responsible for reading the pointer value before modifying it, saving it,
and restoring it before returning from the interrupt.
Typically there would be three processes using the pointer:
1. Transmit loading (sometimes interrupt driven)
2. Receive unloading (interrupt driven)
3. Transmit Status reading (interrupt driven).
1) and 3) also share the usage of the Packet Number Register. Therefore saving and restoring the PNR is also
required from interrupt service routines.
INTERRUPT
'NOT EMPTY'
STATUS REGISTER
RCV
INT
PACKET NUMBER
REGISTER
RX FIFO
PACKET NUMBER
TX EMPTY
INT
TWO
OPTIONS
TX
INT
RX
TX
FIFO
FIFO
ALLOC
INT
'EMPTY'
RX PACKET
NUMBER
TX CO
MPL
ETION
FIFO
'NOT EMPTY'
TX DONE
PACKET NUMBER
CSMA ADDRESS
CPU ADDRESS
CSM
A/C
D
LOG
PACKET
ICAL
#
ADDR
ESS
MM
U
M.S. BIT ONLY
PACK # OUT
PHYS
ICAL
ADD
RESS
RAM
FIGURE 12 - INTERRUPT GENERATION FOR TRANSMIT, RECEIVE, MMU
SMSC DS – LAN91C110 REV. B
Page 45
Rev. 09/05/02