FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications
FUNCTIONAL DESCRIPTION
DESCRIPTION OF BLOCKS
Clock Generator Block
1.
2.
The XTAL1 and XTAL2 pins are to be connected to a 25 MHz 50 PPM crystal.
TX25 is an input clock. It will be the nibble rate of the particular PHY connected to the MII (2.5 MHz for a 10 Mbps
PHY, and 25 MHz for a 100 Mbps PHY).
RX25 - This is the MII nibble rate receive clock used for sampling received data nibbles and running the receive state
machine. (2.5 MHz for a 10 Mbps PHY, and 25 MHz for a 100 Mbps PHY).
3.
CSMA/CD BLOCK
This is a 16 bit oriented block, with fully- independent Transmit and Receive logic. The data path in and out of the block
consists of two 16-bit wide uni-directional FIFOs interfacing the DMA block. The DMA port of the FIFO stores 32 bits to
exploit the 32 bit data path into memory, but the FIFOs themselves are 16 bit wide. The Control Path consists of a set of
registers interfaced to the CPU via the BIU.
DMA Block
This block accesses packet memory on the CSMA/CD’s behalf, fetching transmit data and storing received data. It
interfaces the CSMA/CD Transmit and Receive FIFOs on one side, and the Arbiter block on the other. To increase the
bandwidth into memory, a 50 MHz clock is used by the DMA block, and the data path is 32 bits wide.
For example, during active reception at 100 Mbps, the CSMA/CD block will write a word into the Receive FIFO every
160ns. The DMA will read the FIFO and accumulate two words on the output port to request a memory cycle from the
Arbiter every 320ns.
The DMA machine is able to support full duplex operation. Independent receive and transmit counters are used. Transmit
and receive cycles are alternated when simultaneous receive and transmit accesses are needed.
Arbiter Block
The Arbiter block sequences accesses to packet RAM requested by the BIU and by the DMA blocks. BIU requests
represent pipelined CPU accesses to the Data Register, while DMA requests represent CSMA/CD data movement. The
external memory used is a 25ns SRAM.
The Arbiter is also responsible for controlling the nRWE0-nRWE3 lines as a function of the bytes being written. Read
accesses are always 32 bit wide, and the Arbiter steers the appropriate byte(s) to the appropriate lanes as a function of
the address.
The CPU Data Path consists of two uni-directional FIFOs mapped at the Data Register location. These FIFOs can be
accessed in any combination of bytes, word, or doublewords. The Arbiter will indicate 'Not Ready' whenever a cycle is
initiated that cannot be satisfied by the present state of the FIFO.
SMSC DS – LAN91C110 REV. B
Page 9
Rev. 09/05/02
SMSC [ SMSC CORPORATION ]
