FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications
RX_ER might be asserted during packet reception to signal the LAN91C110 that the present receive packet is invalid. The
LAN91C110 will discard the packet by treating it as a CRC error.
RXD0-RXD3 should always be aligned to packet nibbles, therefore, opening flag detection does not consider misaligned
cases. Opening flag detection expects the 5Dh pattern and will not reject the packet on non-preamble patterns.
CRS100 is used as a frame envelope signal for the CSMA/CD MAC state machines (deferral and backoff functions), but it
is not used for receive framing functions. CRS100 is an asynchronous signal and it will be active whenever there is activity
on the cable, including LAN91C110 transmissions and collisions.
The MII SELECT bit in the CONFIG REGISTER must always be set for proper chip function.
Note that given the modular nature of the MII, TX25 and RX25 cannot be assumed to be free running clocks. The
LAN91C110 will not rely on the presence of TX25 and RX25 during reset and will use its own internal clock whenever a
timeout on TX25 is detected.
MII Management Interface Block
PHY management through the MII management interface is supported by the LAN91C110 by providing the means to
drive a tri-statable data output, a clock, and reading an input. Timing and framing for each management command is to be
generated by the CPU.
SMSC DS – LAN91C110 REV. B
Page 11
Rev. 09/05/02
SMSC [ SMSC CORPORATION ]
